Atmel ATF1508AS Fitter Version 1.8.7.8 ,running Thu Nov 12 17:19:43 2015 fit1508 C:\USERS\VINCE\DOCUMENTS\WEBSVN\TRUNK\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.tt2 -CUPL -dev P1508C84 -JTAG ON ****** Initial fitting strategy and property ****** Pla_in_file = M220A.tt2 Pla_out_file = M220A.tt3 Jedec_file = M220A.jed Vector_file = M220A.tmv verilog_file = M220A.vt Time_file = Log_file = M220A.fit err_file = Device_name = PLCC84 Module_name = Package_type = PLCC Preassign_file = Property_file = Sleep_mode = Preassignment = Security_mode = OFF Pin_keep_mode = ON Dedicated_input_clock = Dedicated_input_reset = Dedicated_input_oe = supporter = CUPL optimize = ON Soft_buffer = Xor_synthesis = OFF Foldback_logic = on Expander = Cascade_logic = OFF Dedicated_input = Output_fast = OFF ******************************* Power down pin 1 = OFF Power down pin 2 = OFF power_reset = OFF JTAG = ON TDI pullup = OFF TMS pullup = OFF MC_power = OFF Open_collector = OFF ITD0 = ON ITD1 = ON ITD2 = ON Fast_inlatch = off ******************************* Info: C:\USERS\VINCE\DOCUMENTS\WEBSVN\TRUNK\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A uses 95% of the pins available in device PLCC84 If you wish to have more pins available for future logic changes Atmel recommends using a larger device --------------------------------------------------------- Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF ... Performing global Output Enable pin assignments ... Performing global pin assignments ... -------------------------------------- Final global control pins assignment (if applicable)... ------------------------------------------------------- Performing input pin pre-assignments ... ------------------------------------ and_h assigned to pin 2 shift_r1 assigned to pin 83 adder0 assigned to pin 1 adder1 assigned to pin 84 Attempt to place floating signals ... ------------------------------------ mem2 is placed at pin 12 (MC 3) pc_enabl is placed at pin 11 (MC 5) da2 is placed at pin 10 (MC 6) da_enabl is placed at pin 9 (MC 8) mem_enabl is placed at pin 8 (MC 11) n_t_5x is placed at feedback node 612 (MC 12) bu1 is placed at pin 6 (MC 13) bv2 is placed at pin 5 (MC 14) n_t_8x is placed at feedback node 615 (MC 15) bv1 is placed at pin 4 (MC 16) data2 is placed at pin 22 (MC 17) io3 is placed at pin 21 (MC 19) mq3_h is placed at pin 20 (MC 21) sc3 is placed at pin 18 (MC 24) data3 is placed at pin 17 (MC 25) ma_enabl is placed at pin 16 (MC 27) br2 is placed at pin 15 (MC 29) n_t_14x is placed at feedback node 631 (MC 31) TDI is placed at pin 14 (MC 32) n_t_12x is placed at feedback node 632 (MC 32) mq2_h is placed at pin 31 (MC 35) ac_low_enabl is placed at pin 30 (MC 37) c0 is placed at pin 29 (MC 38) c2 is placed at pin 28 (MC 40) io2 is placed at pin 27 (MC 43) io_enabl is placed at pin 25 (MC 45) data_enabl is placed at pin 24 (MC 46) TMS is placed at pin 23 (MC 48) sr_enabl is placed at pin 41 (MC 49) sr3 is placed at pin 40 (MC 51) sc2 is placed at pin 39 (MC 53) be2 is placed at pin 37 (MC 56) sr2 is placed at pin 36 (MC 57) sc_enabl is placed at pin 35 (MC 59) mq_enabl is placed at pin 34 (MC 61) ac_enabl is placed at pin 33 (MC 64) ac2_l is placed at pin 44 (MC 65) ac2_h is placed at pin 45 (MC 67) ac3_h is placed at pin 46 (MC 69) ac3_l is placed at pin 48 (MC 72) au1 is placed at pin 49 (MC 73) au2 is placed at pin 50 (MC 75) at2 is placed at pin 51 (MC 77) as1 is placed at pin 52 (MC 80) as2 is placed at pin 54 (MC 83) ar1 is placed at pin 55 (MC 85) pc2_l is placed at pin 56 (MC 86) pc2_h is placed at pin 57 (MC 88) pc3_l is placed at pin 58 (MC 91) pc3_h is placed at pin 60 (MC 93) an2 is placed at pin 61 (MC 94) TCK is placed at pin 62 (MC 96) ma2_l is placed at pin 63 (MC 97) ma2_h is placed at pin 64 (MC 99) ma3_l is placed at pin 65 (MC 101) ma3_h is placed at pin 67 (MC 104) ak1 is placed at pin 68 (MC 105) ak2 is placed at pin 69 (MC 107) aj1 is placed at pin 70 (MC 109) TDO is placed at pin 71 (MC 112) adder5 is placed at pin 73 (MC 115) shift_l2 is placed at pin 74 (MC 117) adder4 is placed at pin 75 (MC 118) adder3 is placed at pin 76 (MC 120) shift_l1 is placed at pin 77 (MC 123) no_shift is placed at pin 79 (MC 125) adder2 is placed at pin 80 (MC 126) shift_r2 is placed at pin 81 (MC 128) m p d e s s n s c a m h h o h _ _ _ aa i i a _ i a a e e e a dd f f d s f d d n n n n dd t t d h t d d a d a a G b b b V d ee _ G _ e i V _ e e b a b b N u v v C _ rr r N r r f C l r r l 2 l l D 1 2 1 C h 01 1 D 2 2 t C 1 3 4 ------------------------------------------- / 11 9 7 5 3 1 83 81 79 77 75 \ / 10 8 6 4 2 84 82 80 78 76 \ mem2 | 12 (*) 74 | shift_l2 VCC | 13 73 | adder5 TDI | 14 72 | GND br2 | 15 71 | TDO ma_enabl | 16 70 | aj1 data3 | 17 69 | ak2 sc3 | 18 68 | ak1 GND | 19 67 | ma3_h mq3_h | 20 66 | VCC io3 | 21 65 | ma3_l data2 | 22 ATF1508 64 | ma2_h TMS | 23 84-Lead PLCC 63 | ma2_l data_enabl | 24 62 | TCK io_enabl | 25 61 | an2 VCC | 26 60 | pc3_h io2 | 27 59 | GND c2 | 28 58 | pc3_l c0 | 29 57 | pc2_h ac_low_enabl | 30 56 | pc2_l mq2_h | 31 55 | ar1 GND | 32 54 | as2 \ 34 36 38 40 42 44 46 48 50 52 / \ 33 35 37 39 41 43 45 47 49 51 53/ -------------------------------------------- a m s s b V s s s G V a a a G a a a a a V c q c r e C c r r N C c c c N c u u t s C _ _ _ 2 2 C 2 3 _ D C 2 2 3 D 3 1 2 2 1 C e e e e _ _ _ _ n n n n l h h l a a a a b b b b l l l l VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V) GND = GND pin which must be connected to ground TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface NC = Unused I/O pins which must be unconnected on the board Universal-Interconnect-Multiplexer assignments ------------------------------------------------ FanIn assignment for block A [20] { ac3_h,ac2_h,ac_enabl,ac_low_enabl, be2, data2,data3,data_enabl, io_enabl,io2,io3, mq_enabl,mq3_h,mq2_h, sr2,sr_enabl,sc2,sc3,sc_enabl,sr3, } Multiplexer assignment for block A be2 (MC13 P) : MUX 1 Ref (D56p) sr2 (MC19 P) : MUX 4 Ref (D57p) sr_enabl (MC10 P) : MUX 5 Ref (D49p) mq_enabl (MC6 P) : MUX 8 Ref (D61p) ac3_h (MC2 P) : MUX 9 Ref (E69p) ac2_h (MC1 P) : MUX 11 Ref (E67p) ac_enabl (MC12 P) : MUX 12 Ref (D64p) io_enabl (MC4 P) : MUX 14 Ref (C45p) data2 (MC20 P) : MUX 15 Ref (B17p) data3 (MC14 P) : MUX 16 Ref (B25p) sc2 (MC18 P) : MUX 17 Ref (D53p) io2 (MC16 P) : MUX 18 Ref (C43p) ac_low_enabl (MC11 P) : MUX 19 Ref (C37p) data_enabl (MC15 P) : MUX 20 Ref (C46p) sc3 (MC7 P) : MUX 23 Ref (B24p) sc_enabl (MC8 P) : MUX 26 Ref (D59p) sr3 (MC9 P) : MUX 27 Ref (D51p) io3 (MC3 P) : MUX 29 Ref (B19p) mq3_h (MC5 P) : MUX 33 Ref (B21p) mq2_h (MC17 P) : MUX 35 Ref (C35p) FanIn assignment for block B [14] { bu1,bv1,bv2,br2, da_enabl,da2, ma_enabl,ma2_h,mem_enabl,mem2,ma3_h, pc_enabl,pc3_h,pc2_h, } Multiplexer assignment for block B bu1 (MC11 P) : MUX 0 Ref (A13p) pc_enabl (MC8 P) : MUX 1 Ref (A5p) ma_enabl (MC5 P) : MUX 2 Ref (B27p) da_enabl (MC10 P) : MUX 3 Ref (A8p) pc3_h (MC2 P) : MUX 4 Ref (F93p) ma2_h (MC3 P) : MUX 5 Ref (G99p) bv1 (MC13 P) : MUX 10 Ref (A16p) bv2 (MC14 P) : MUX 12 Ref (A14p) br2 (MC12 P) : MUX 14 Ref (B29p) da2 (MC9 P) : MUX 15 Ref (A6p) pc2_h (MC1 P) : MUX 17 Ref (F88p) mem_enabl (MC7 P) : MUX 24 Ref (A11p) mem2 (MC6 P) : MUX 29 Ref (A3p) ma3_h (MC4 P) : MUX 31 Ref (G104p) FanIn assignment for block C [5] { c0, n_t_5x,n_t_8x,n_t_14x,n_t_12x, } Multiplexer assignment for block C n_t_5x (MC1 FB) : MUX 1 Ref (A12fb) n_t_8x (MC2 FB) : MUX 5 Ref (A15fb) c0 (MC5 P) : MUX 7 Ref (C38p) n_t_14x (MC3 FB) : MUX 25 Ref (B31fb) n_t_12x (MC4 FB) : MUX 37 Ref (B32fb) FanIn assignment for block E [8] { au1,as2,aj1,ac3_h,ak2,ac2_h,at2,ar1, } Multiplexer assignment for block E au1 (MC8 P) : MUX 0 Ref (E73p) as2 (MC4 P) : MUX 1 Ref (F83p) aj1 (MC6 P) : MUX 6 Ref (G109p) ac3_h (MC2 P) : MUX 11 Ref (E69p) ak2 (MC5 P) : MUX 12 Ref (G107p) ac2_h (MC1 P) : MUX 15 Ref (E67p) at2 (MC3 P) : MUX 16 Ref (E77p) ar1 (MC7 P) : MUX 23 Ref (F85p) FanIn assignment for block F [6] { aj1,ar1,ak2,an2, pc2_h,pc3_h, } Multiplexer assignment for block F pc2_h (MC1 P) : MUX 3 Ref (F88p) aj1 (MC4 P) : MUX 4 Ref (G109p) ar1 (MC5 P) : MUX 5 Ref (F85p) ak2 (MC3 P) : MUX 12 Ref (G107p) pc3_h (MC2 P) : MUX 18 Ref (F93p) an2 (MC6 P) : MUX 22 Ref (F94p) FanIn assignment for block G [19] { as2,aj1,adder4,ak2,adder5,adder0,and_h,at2,adder3,ak1,adder1,adder2, ma2_h,ma3_h, no_shift, shift_r2,shift_r1,shift_l2,shift_l1, } Multiplexer assignment for block G shift_r2 (MC16 P) : MUX 0 Ref (H128p) as2 (MC2 P) : MUX 1 Ref (F83p) ma2_h (MC3 P) : MUX 5 Ref (G99p) aj1 (MC6 P) : MUX 6 Ref (G109p) adder4 (MC10 P) : MUX 7 Ref (H118p) no_shift (MC9 P) : MUX 8 Ref (H125p) ak2 (MC5 P) : MUX 12 Ref (G107p) adder5 (MC12 P) : MUX 13 Ref (H115p) adder0 (MC18 FB) : MUX 14 Ref (GCLR) ma3_h (MC4 P) : MUX 15 Ref (G104p) and_h (MC17 FB) : MUX 16 Ref (OE2) shift_r1 (MC14 FB) : MUX 17 Ref (GCLK) at2 (MC1 P) : MUX 18 Ref (E77p) adder3 (MC7 P) : MUX 19 Ref (H120p) shift_l2 (MC13 P) : MUX 21 Ref (H117p) ak1 (MC19 P) : MUX 24 Ref (G105p) adder1 (MC15 FB) : MUX 25 Ref (OE1) shift_l1 (MC11 P) : MUX 26 Ref (H123p) adder2 (MC8 P) : MUX 28 Ref (H126p) FanIn assignment for block H [5] { c0, n_t_5x,n_t_8x,n_t_14x,n_t_12x, } Multiplexer assignment for block H n_t_5x (MC1 FB) : MUX 1 Ref (A12fb) n_t_8x (MC2 FB) : MUX 5 Ref (A15fb) c0 (MC5 P) : MUX 7 Ref (C38p) n_t_14x (MC3 FB) : MUX 25 Ref (B31fb) n_t_12x (MC4 FB) : MUX 37 Ref (B32fb) Creating JEDEC file C:\USERS\VINCE\DOCUMENTS\WEBSVN\TRUNK\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.jed ... PLCC84 programmed logic: ----------------------------------- ac3_l = !ac3_h.Q; ac2_l = !ac2_h.Q; au2 = !at2.Q; as1 = !as2.Q; ma2_l = !ma2_h.Q; ma3_l = !ma3_h.Q; n_t_12x = ((ma2_h.Q & ma_enabl) # (mem2 & mem_enabl) # (pc2_h.Q & pc_enabl) # (da2 & da_enabl)); n_t_14x = ((bu1 & da_enabl) # (br2 & ma3_h.Q) # (pc3_h.Q & pc_enabl) # (bv1 & bv2)); pc2_l = !pc2_h.Q; pc3_l = !pc3_h.Q; n_t_5x = ((io2 & io_enabl) # (mq2_h & mq_enabl) # (sc2 & sc_enabl) # (sr2 & sr_enabl) # (!ac2_h.Q & ac_low_enabl) # (ac2_h.Q & ac_enabl) # (data2 & data_enabl)); n_t_8x = ((io3 & io_enabl) # (mq3_h & mq_enabl) # (sc3 & sc_enabl) # (sr3 & sr_enabl) # (!ac3_h.Q & ac_low_enabl) # (ac3_h.Q & ac_enabl) # be2 # (data3 & data_enabl)); !adder2 = ((c0 & n_t_12x & !n_t_14x & !n_t_5x) # (!c0 & !n_t_12x & n_t_14x & !n_t_5x) # (c0 & !n_t_12x & !n_t_14x & n_t_5x) # (!c0 & n_t_12x & n_t_14x & n_t_5x) # (c0 & n_t_12x & !n_t_5x & !n_t_8x) # (n_t_12x & !n_t_14x & !n_t_5x & !n_t_8x) # (c0 & !n_t_12x & n_t_5x & !n_t_8x) # (!n_t_12x & !n_t_14x & n_t_5x & !n_t_8x) # (!c0 & !n_t_12x & !n_t_5x & n_t_8x) # (!n_t_12x & n_t_14x & !n_t_5x & n_t_8x) # (!c0 & n_t_12x & n_t_5x & n_t_8x) # (n_t_12x & n_t_14x & n_t_5x & n_t_8x)); adder3 = ((c0 & !n_t_14x & !n_t_8x) # (!c0 & !n_t_14x & n_t_8x) # (!c0 & n_t_14x & !n_t_8x) # (c0 & n_t_14x & n_t_8x)); c2 = ((!n_t_14x & !n_t_5x & c0) # (!n_t_5x & !n_t_12x) # (!n_t_14x & !n_t_5x & !n_t_8x) # (!n_t_14x & !n_t_8x & !n_t_12x) # (!n_t_5x & !n_t_8x & c0) # (!n_t_8x & c0 & !n_t_12x) # (!n_t_14x & c0 & !n_t_12x)); !aj1 = ((adder2 & no_shift) # (adder3 & shift_l1) # (adder4 & shift_l2) # (adder1 & shift_r1) # (adder0 & shift_r2) # (and_h & !at2.Q)); !ak2 = ((adder3 & no_shift) # (adder4 & shift_l1) # (adder5 & shift_l2) # (adder2 & shift_r1) # (adder1 & shift_r2) # (and_h & !as2.Q)); ac2_h.D = aj1; ac3_h.D = ak2; ma2_h.D = aj1; as2.D = ak2; ma3_h.D = ak2; at2.D = aj1; pc2_h.D = aj1; pc3_h.D = ak2; ac2_h.C = au1; ac3_h.C = au1; ma2_h.C = ak1; as2.C = ar1; ma3_h.C = ak1; at2.C = ar1; pc2_h.C = an2; pc3_h.C = an2; PLCC84 Pin/Node Placement: ------------------------------------ Pin 1 = adder0; Pin 2 = and_h; Pin 4 = bv1; /* MC 16 */ Pin 5 = bv2; /* MC 14 */ Pin 6 = bu1; /* MC 13 */ Pin 8 = mem_enabl; /* MC 11 */ Pin 9 = da_enabl; /* MC 8 */ Pin 10 = da2; /* MC 6 */ Pin 11 = pc_enabl; /* MC 5 */ Pin 12 = mem2; /* MC 3 */ Pin 14 = TDI; /* MC 32 */ Pin 15 = br2; /* MC 29 */ Pin 16 = ma_enabl; /* MC 27 */ Pin 17 = data3; /* MC 25 */ Pin 18 = sc3; /* MC 24 */ Pin 20 = mq3_h; /* MC 21 */ Pin 21 = io3; /* MC 19 */ Pin 22 = data2; /* MC 17 */ Pin 23 = TMS; /* MC 48 */ Pin 24 = data_enabl; /* MC 46 */ Pin 25 = io_enabl; /* MC 45 */ Pin 27 = io2; /* MC 43 */ Pin 28 = c2; /* MC 40 */ Pin 29 = c0; /* MC 38 */ Pin 30 = ac_low_enabl; /* MC 37 */ Pin 31 = mq2_h; /* MC 35 */ Pin 33 = ac_enabl; /* MC 64 */ Pin 34 = mq_enabl; /* MC 61 */ Pin 35 = sc_enabl; /* MC 59 */ Pin 36 = sr2; /* MC 57 */ Pin 37 = be2; /* MC 56 */ Pin 39 = sc2; /* MC 53 */ Pin 40 = sr3; /* MC 51 */ Pin 41 = sr_enabl; /* MC 49 */ Pin 44 = ac2_l; /* MC 65 */ Pin 45 = ac2_h; /* MC 67 */ Pin 46 = ac3_h; /* MC 69 */ Pin 48 = ac3_l; /* MC 72 */ Pin 49 = au1; /* MC 73 */ Pin 50 = au2; /* MC 75 */ Pin 51 = at2; /* MC 77 */ Pin 52 = as1; /* MC 80 */ Pin 54 = as2; /* MC 83 */ Pin 55 = ar1; /* MC 85 */ Pin 56 = pc2_l; /* MC 86 */ Pin 57 = pc2_h; /* MC 88 */ Pin 58 = pc3_l; /* MC 91 */ Pin 60 = pc3_h; /* MC 93 */ Pin 61 = an2; /* MC 94 */ Pin 62 = TCK; /* MC 96 */ Pin 63 = ma2_l; /* MC 97 */ Pin 64 = ma2_h; /* MC 99 */ Pin 65 = ma3_l; /* MC 101 */ Pin 67 = ma3_h; /* MC 104 */ Pin 68 = ak1; /* MC 105 */ Pin 69 = ak2; /* MC 107 */ Pin 70 = aj1; /* MC 109 */ Pin 71 = TDO; /* MC 112 */ Pin 73 = adder5; /* MC 115 */ Pin 74 = shift_l2; /* MC 117 */ Pin 75 = adder4; /* MC 118 */ Pin 76 = adder3; /* MC 120 */ Pin 77 = shift_l1; /* MC 123 */ Pin 79 = no_shift; /* MC 125 */ Pin 80 = adder2; /* MC 126 */ Pin 81 = shift_r2; /* MC 128 */ Pin 83 = shift_r1; Pin 84 = adder1; PINNODE 612 = n_t_5x; /* MC 12 Feedback */ PINNODE 615 = n_t_8x; /* MC 15 Feedback */ PINNODE 631 = n_t_14x; /* MC 31 Feedback */ PINNODE 632 = n_t_12x; /* MC 32 Feedback */ ** Resource Usage ** DCERP Field = Summary of Allocations. ||||| |||||_Preset [p,-] == p = PT preset, - No Preset. |||| ||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset. ||| |||___Clock Enable [e,-] == e = Product Term, - always enabled, - none. || ||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock. | |_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff. For input only = INPUT. MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT output_slew MC1 0 -- -- -- -- 0 slow MC2 0 -- -- -- -- 0 slow MC3 12 -- mem2 INPUT -- -- -- 0 slow MC4 0 -- -- -- -- 0 slow MC5 11 -- pc_enabl INPUT -- -- -- 0 slow MC6 10 -- da2 INPUT -- -- -- 0 slow MC7 0 -- -- -- -- 0 slow MC8 9 -- da_enabl INPUT -- -- -- 0 slow MC9 0 -- -- -- -- 0 slow MC10 0 -- -- -- -- 0 slow MC11 8 -- mem_enabl INPUT -- -- -> n_t_5x 5 slow MC12 0 -- n_t_5x C---- -- -- 2 slow MC13 6 -- bu1 INPUT -- -- -- 0 slow MC14 5 -- bv2 INPUT -- -- -> n_t_8x 5 slow MC15 0 -- n_t_8x C---- -- -- 3 slow MC16 4 -- bv1 INPUT -- -- -- 0 slow MC17 22 -- data2 INPUT -- -- -- 0 slow MC18 0 -- -- -- -- 0 slow MC19 21 -- io3 INPUT -- -- -- 0 slow MC20 0 -- -- -- -- 0 slow MC21 20 -- mq3_h INPUT -- -- -- 0 slow MC22 0 -- -- -- -- 0 slow MC23 0 -- -- -- -- 0 slow MC24 18 -- sc3 INPUT -- -- -- 0 slow MC25 17 -- data3 INPUT -- -- -- 0 slow MC26 0 -- -- -- -- 0 slow MC27 16 -- ma_enabl INPUT -- -- -- 0 slow MC28 0 -- -- -- -- 0 slow MC29 15 -- br2 INPUT -- -- -- 0 slow MC30 0 -- -- -- -- 0 slow MC31 0 -- n_t_14x C---- -- -- 4 slow MC32 14 -- TDI INPUT n_t_12x C---- -- -- 4 slow MC33 0 -- -- -- -- 0 slow MC34 0 -- -- -- -- 0 slow MC35 31 -- mq2_h INPUT -- -- -- 0 slow MC36 0 -- -- -- -- 0 slow MC37 30 -- ac_low_enabl INPUT -- -- -- 0 slow MC38 29 -- c0 INPUT -- -- -- 0 slow MC39 0 -- -- -- -> c2 5 slow MC40 28 on c2 C---- -- -- -- 2 slow MC41 0 -- -- -- -- 0 slow MC42 0 -- -- -- -- 0 slow MC43 27 -- io2 INPUT -- -- -- 0 slow MC44 0 -- -- -- -- 0 slow MC45 25 -- io_enabl INPUT -- -- -- 0 slow MC46 24 -- data_enabl INPUT -- -- -- 0 slow MC47 0 -- -- -- -- 0 slow MC48 23 -- TMS INPUT -- -- -- 0 slow MC49 41 -- sr_enabl INPUT -- -- -- 0 slow MC50 0 -- -- -- -- 0 slow MC51 40 -- sr3 INPUT -- -- -- 0 slow MC52 0 -- -- -- -- 0 slow MC53 39 -- sc2 INPUT -- -- -- 0 slow MC54 0 -- -- -- -- 0 slow MC55 0 -- -- -- -- 0 slow MC56 37 -- be2 INPUT -- -- -- 0 slow MC57 36 -- sr2 INPUT -- -- -- 0 slow MC58 0 -- -- -- -- 0 slow MC59 35 -- sc_enabl INPUT -- -- -- 0 slow MC60 0 -- -- -- -- 0 slow MC61 34 -- mq_enabl INPUT -- -- -- 0 slow MC62 0 -- -- -- -- 0 slow MC63 0 -- -- -- -- 0 slow MC64 33 -- ac_enabl INPUT -- -- -- 0 slow MC65 44 on ac2_l C---- -- -- -- 1 slow MC66 0 -- -- -- -- 0 slow MC67 45 on ac2_h Dc--- -- -- -- 2 slow MC68 0 -- -- -- -- 0 slow MC69 46 on ac3_h Dc--- -- -- -- 2 slow MC70 0 -- -- -- -- 0 slow MC71 0 -- -- -- -- 0 slow MC72 48 on ac3_l C---- -- -- -- 1 slow MC73 49 -- au1 INPUT -- -- -- 0 slow MC74 0 -- -- -- -- 0 slow MC75 50 on au2 C---- -- -- -- 1 slow MC76 0 -- -- -- -- 0 slow MC77 51 on at2 Dc--- -- -- -- 2 slow MC78 0 -- -- -- -- 0 slow MC79 0 -- -- -- -- 0 slow MC80 52 on as1 C---- -- -- -- 1 slow MC81 0 -- -- -- -- 0 slow MC82 0 -- -- -- -- 0 slow MC83 54 on as2 Dc--- -- -- -- 2 slow MC84 0 -- -- -- -- 0 slow MC85 55 -- ar1 INPUT -- -- -- 0 slow MC86 56 on pc2_l C---- -- -- -- 1 slow MC87 0 -- -- -- -- 0 slow MC88 57 on pc2_h Dc--- -- -- -- 2 slow MC89 0 -- -- -- -- 0 slow MC90 0 -- -- -- -- 0 slow MC91 58 on pc3_l C---- -- -- -- 1 slow MC92 0 -- -- -- -- 0 slow MC93 60 on pc3_h Dc--- -- -- -- 2 slow MC94 61 -- an2 INPUT -- -- -- 0 slow MC95 0 -- -- -- -- 0 slow MC96 62 -- TCK INPUT -- -- -- 0 slow MC97 63 on ma2_l C---- -- -- -- 1 slow MC98 0 -- -- -- -- 0 slow MC99 64 on ma2_h Dc--- -- -- -- 2 slow MC100 0 -- -- -- -- 0 slow MC101 65 on ma3_l C---- -- -- -- 1 slow MC102 0 -- -- -- -- 0 slow MC103 0 -- -- -- -- 0 slow MC104 67 on ma3_h Dc--- -- -- -- 2 slow MC105 68 -- ak1 INPUT -- -- -- 0 slow MC106 0 -- -- -- -> ak2 5 slow MC107 69 on ak2 C---- -- -- -- 1 slow MC108 0 -- -- -- -> aj1 5 slow MC109 70 on aj1 C---- -- -- -- 1 slow MC110 0 -- -- -- -- 0 slow MC111 0 -- -- -- -- 0 slow MC112 71 -- TDO INPUT -- -- -- 0 slow MC113 0 -- -- -- -- 0 slow MC114 0 -- -- -- -- 0 slow MC115 73 -- adder5 INPUT -- -- -- 0 slow MC116 0 -- -- -- -- 0 slow MC117 74 -- shift_l2 INPUT -- -- -- 0 slow MC118 75 -- adder4 INPUT -- -- -- 0 slow MC119 0 -- -- -- -- 0 slow MC120 76 on adder3 C---- -- -- -- 4 slow MC121 0 -- -- -- -- 0 slow MC122 0 -- -- -- -- 0 slow MC123 77 -- shift_l1 INPUT -- -- -- 0 slow MC124 0 -- -- -- -> adder2 5 slow MC125 79 -- no_shift INPUT -- -- -> adder2 5 slow MC126 80 on adder2 C---- -- -- -- 2 slow MC127 0 -- -- -- -- 0 slow MC128 81 -- shift_r2 INPUT -- -- -- 0 slow MC0 2 and_h INPUT -- -- -- 0 slow MC0 1 adder0 INPUT -- -- -- 0 slow MC0 84 adder1 INPUT -- -- -- 0 slow MC0 83 shift_r1 INPUT -- -- -- 0 slow Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades A: LC1 - LC16 2/16(12%) 8/16(50%) 0/16(0%) 15/80(18%) (20) 2 B: LC17 - LC32 2/16(12%) 8/16(50%) 0/16(0%) 8/80(10%) (14) 0 C: LC33 - LC48 1/16(6%) 8/16(50%) 0/16(0%) 7/80(8%) (5) 1 D: LC49 - LC64 0/16(0%) 8/16(50%) 0/16(0%) 0/80(0%) (8) 0 E: LC65 - LC80 7/16(43%) 8/16(50%) 0/16(0%) 10/80(12%) (6) 0 F: LC81 - LC96 5/16(31%) 8/16(50%) 0/16(0%) 8/80(10%) (19) 0 G: LC97 - LC112 6/16(37%) 8/16(50%) 0/16(0%) 18/80(22%) (5) 2 H: LC113- LC128 2/16(12%) 8/16(50%) 0/16(0%) 16/80(20%) (5) 2 Total dedicated input used: 4/4 (100%) Total I/O pins used 64/64 (100%) Total Logic cells used 32/128 (25%) Total Flip-Flop used 8/128 (6%) Total Foldback logic used 0/128 (0%) Total Nodes+FB/MCells 25/128 (19%) Total cascade used 7 Total input pins 47 Total output pins 21 Total Pts 82 Creating pla file C:\USERS\VINCE\DOCUMENTS\WEBSVN\TRUNK\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms... ---------------- End fitter, Design FITS $Device PLCC84 fits FIT1508 completed in 0.00 seconds