cpldfit: version H.38 Xilinx Inc. Fitter Report Design Name: m220 Date: 5-11-2011, 10:53PM Device Used: XC9536XL-5-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 8 /36 ( 22%) 99 /180 ( 55%) 32 /108 ( 30%) 4 /36 ( 11%) 9 /34 ( 26%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 4/18 18/54 58/90 2/17 FB2 4/18 14/54 41/90 4/17 ----- ----- ----- ----- 8/36 32/108 99/180 6/34 * - Resource is exhausted ** Global Control Resources ** Signal 'ac_load' mapped onto global clock net GCK1. Signal 'ma_load' mapped onto global clock net GCK2. Signal 'mb_load' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 24 24 | I/O : 27 28 Output : 6 6 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 3 3 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 33 33 ** Power Data ** There are 8 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 6 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State carry_out_ 25 17 FB1_4 4 I/O O STD FAST adder_ 22 9 FB1_12 14 I/O O STD FAST pc 11 14 FB2_2 44 I/O O STD FAST RESET ac 10 13 FB2_7 38 I/O O STD FAST RESET ma 10 13 FB2_12 33 I/O O STD FAST RESET mb 10 13 FB2_16 26 I/O O STD FAST RESET ** 2 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State _n0012/_n0012_D2 4 7 FB1_17 STD a_/a__D2 7 9 FB1_18 STD ** 27 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use b_src0 FB1_1 2 I/O I input_bus FB1_2 3 I/O I ac_load FB1_3 5~ GCK/I/O GCK ma_load FB1_5 6~ GCK/I/O GCK shift1 FB1_6 8 I/O I mb_load FB1_7 7~ GCK/I/O GCK sc FB1_8 9 I/O I sr FB1_9 11 I/O I shift2 FB1_11 13 I/O I shift0 FB1_13 18 I/O I pc_load FB1_14 19 I/O I mq FB1_15 20 I/O I mem FB1_16 22 I/O I b_src2 FB1_17 24 I/O I and_enable FB2_1 1 I/O I adder_left2_ FB2_3 42 GTS/I/O I data_addr FB2_4 43 I/O I adder_left1_ FB2_5 40 GTS/I/O I carry_in_ FB2_6 39 GSR/I/O I a_src0 FB2_8 37 I/O I b_src1 FB2_9 36 I/O I data FB2_10 35 I/O I a_src1 FB2_11 34 I/O I a_src2 FB2_13 29 I/O I adder_right1_ FB2_14 28 I/O I adder_right2_ FB2_15 27 I/O I tt_ls_in FB2_17 25 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\1 4 FB1_1 2 I/O I (unused) 0 0 \/5 0 FB1_2 3 I/O I (unused) 0 0 \/5 0 FB1_3 5 GCK/I/O GCK carry_out_ 25 20<- 0 0 FB1_4 4 I/O O (unused) 0 0 /\5 0 FB1_5 6 GCK/I/O GCK (unused) 0 0 /\5 0 FB1_6 8 I/O I (unused) 0 0 0 5 FB1_7 7 GCK/I/O GCK (unused) 0 0 0 5 FB1_8 9 I/O I (unused) 0 0 0 5 FB1_9 11 I/O I (unused) 0 0 \/4 1 FB1_10 12 I/O (b) (unused) 0 0 \/5 0 FB1_11 13 I/O I adder_ 22 17<- 0 0 FB1_12 14 I/O O (unused) 0 0 /\5 0 FB1_13 18 I/O I (unused) 0 0 /\3 2 FB1_14 19 I/O I (unused) 0 0 0 5 FB1_15 20 I/O I (unused) 0 0 0 5 FB1_16 22 I/O I _n0012/_n0012_D2 4 0 \/1 0 FB1_17 24 I/O I a_/a__D2 7 2<- 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: a_/a__D2 7: b_src1 13: ma 2: a_src0 8: b_src2 14: mem 3: a_src1 9: carry_in_ 15: mq 4: a_src2 10: data 16: pc 5: ac 11: data_addr 17: sc 6: b_src0 12: input_bus 18: sr Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs carry_out_ .XXXXXXXXXXXXXXXXX...................... 17 adder_ X....XXXX.X.XX.X........................ 9 _n0012/_n0012_D2 .....XXX..X.XX.X........................ 7 a_/a__D2 .XXXX....X.X..X.XX...................... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 14/40 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/3 2 FB2_1 1 I/O I pc 11 6<- 0 0 FB2_2 44 I/O O (unused) 0 0 /\3 2 FB2_3 42 GTS/I/O I (unused) 0 0 0 5 FB2_4 43 I/O I (unused) 0 0 0 5 FB2_5 40 GTS/I/O I (unused) 0 0 \/3 2 FB2_6 39 GSR/I/O I ac 10 5<- 0 0 FB2_7 38 I/O O (unused) 0 0 /\2 3 FB2_8 37 I/O I (unused) 0 0 0 5 FB2_9 36 I/O I (unused) 0 0 0 5 FB2_10 35 I/O I (unused) 0 0 \/3 2 FB2_11 34 I/O I ma 10 5<- 0 0 FB2_12 33 I/O O (unused) 0 0 /\2 3 FB2_13 29 I/O I (unused) 0 0 0 5 FB2_14 28 I/O I (unused) 0 0 \/3 2 FB2_15 27 I/O I mb 10 5<- 0 0 FB2_16 26 I/O O (unused) 0 0 /\2 3 FB2_17 25 I/O I (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: _n0012/_n0012_D2 6: adder_right2_ 11: shift0 2: a_/a__D2 7: and_enable 12: shift1 3: adder_left1_ 8: carry_in_ 13: shift2 4: adder_left2_ 9: mb 14: tt_ls_in 5: adder_right1_ 10: pc_load Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs pc XXXXXXXXXXXXXX.......................... 14 ac XXXXXXXXX.XXXX.......................... 13 ma XXXXXXXXX.XXXX.......................... 13 mb XXXXXXXXX.XXXX.......................... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** _n0012/_n0012_D2 = ma & !b_src1 & b_src2 & !b_src0 # pc & b_src1 & !b_src2 & !b_src0 # mem & b_src1 & b_src2 & !b_src0 # !b_src1 & !b_src2 & b_src0 & data_addr; a_/a__D2 = !a_src2 & !a_src1 & !sr # !a_src2 & ac & !a_src0 # !a_src1 & !ac & !a_src0 # a_src2 & !sc & !a_src1 & a_src0 # a_src2 & a_src1 & !mq & !a_src0 ;Imported pterms FB1_1 # !a_src2 & a_src1 & !data & a_src0 ;Imported pterms FB1_17 # a_src2 & a_src1 & !input_bus & a_src0; !ac.D = !mb & and_enable # shift0 & !shift1 & !shift2 & adder_left2_ # !shift0 & shift1 & adder_right2_ & !shift2 # !shift0 & shift1 & shift2 & adder_left1_ # !shift0 & !shift1 & shift2 & adder_right1_ ;Imported pterms FB2_6 # shift0 & !shift1 & shift2 & tt_ls_in # carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & a_/a__D2 ;Imported pterms FB2_8 # carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & !a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & !a_/a__D2; ac.CLK = ac_load; // GCK adder_ = carry_in_ & b_src0 & !data_addr & !a_/a__D2 # !carry_in_ & b_src0 & !data_addr & a_/a__D2 # carry_in_ & !ma & !b_src1 & !b_src0 & !a_/a__D2 # carry_in_ & !pc & !b_src2 & !b_src0 & !a_/a__D2 # !carry_in_ & !ma & !b_src1 & !b_src0 & a_/a__D2 ;Imported pterms FB1_11 # carry_in_ & b_src1 & b_src0 & !a_/a__D2 # carry_in_ & b_src2 & b_src0 & !a_/a__D2 # !carry_in_ & b_src1 & b_src0 & a_/a__D2 # !carry_in_ & b_src2 & b_src0 & a_/a__D2 # !carry_in_ & !pc & !b_src2 & !b_src0 & a_/a__D2 ;Imported pterms FB1_10 # carry_in_ & ma & !b_src1 & b_src2 & !b_src0 & a_/a__D2 # carry_in_ & mem & b_src1 & b_src2 & !b_src0 & a_/a__D2 # carry_in_ & !b_src1 & !b_src2 & b_src0 & data_addr & a_/a__D2 # !carry_in_ & pc & b_src1 & !b_src2 & !b_src0 & !a_/a__D2 ;Imported pterms FB1_13 # carry_in_ & !mem & b_src1 & b_src2 & !a_/a__D2 # carry_in_ & !b_src1 & !b_src2 & !b_src0 & !a_/a__D2 # !carry_in_ & !mem & b_src1 & b_src2 & a_/a__D2 # !carry_in_ & !b_src1 & !b_src2 & !b_src0 & a_/a__D2 # carry_in_ & pc & b_src1 & !b_src2 & !b_src0 & a_/a__D2 ;Imported pterms FB1_14 # !carry_in_ & ma & !b_src1 & b_src2 & !b_src0 & !a_/a__D2 # !carry_in_ & mem & b_src1 & b_src2 & !b_src0 & !a_/a__D2 # !carry_in_ & !b_src1 & !b_src2 & b_src0 & data_addr & !a_/a__D2; !carry_out_ = !carry_in_ & b_src0 & !data_addr # carry_in_ & ma & !b_src1 & b_src2 & !b_src0 # carry_in_ & pc & b_src1 & !b_src2 & !b_src0 # carry_in_ & mem & b_src1 & b_src2 & !b_src0 # carry_in_ & !b_src1 & !b_src2 & b_src0 & data_addr ;Imported pterms FB1_3 # !carry_in_ & b_src1 & b_src0 # !carry_in_ & !ma & !b_src1 & !b_src0 # !carry_in_ & !mem & b_src1 & b_src2 # carry_in_ & a_src2 & a_src1 & mq & !a_src0 # carry_in_ & !a_src2 & !a_src1 & sr & a_src0 ;Imported pterms FB1_2 # !carry_in_ & !a_src2 & !a_src1 & !sr # !carry_in_ & a_src2 & !sc & !a_src1 & a_src0 # !carry_in_ & a_src2 & a_src1 & !input_bus & a_src0 # !carry_in_ & a_src2 & a_src1 & !mq & !a_src0 # !carry_in_ & !a_src2 & a_src1 & !data & a_src0 ;Imported pterms FB1_5 # carry_in_ & a_src2 & sc & !a_src1 & a_src0 # carry_in_ & a_src2 & a_src1 & input_bus & a_src0 # carry_in_ & a_src2 & !a_src1 & ac & !a_src0 # carry_in_ & !a_src2 & a_src1 & !ac & !a_src0 # carry_in_ & !a_src2 & a_src1 & data & a_src0 ;Imported pterms FB1_6 # !carry_in_ & b_src2 & b_src0 # !carry_in_ & !a_src2 & ac & !a_src0 # !carry_in_ & !a_src1 & !ac & !a_src0 # !carry_in_ & !pc & b_src1 & !b_src2 # !carry_in_ & !b_src1 & !b_src2 & !b_src0; !ma.D = !mb & and_enable # shift0 & !shift1 & !shift2 & adder_left2_ # !shift0 & shift1 & adder_right2_ & !shift2 # !shift0 & shift1 & shift2 & adder_left1_ # !shift0 & !shift1 & shift2 & adder_right1_ ;Imported pterms FB2_11 # shift0 & !shift1 & shift2 & tt_ls_in # carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & a_/a__D2 ;Imported pterms FB2_13 # carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & !a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & !a_/a__D2; ma.CLK = ma_load; // GCK !mb.D = !mb & and_enable # shift0 & !shift1 & !shift2 & adder_left2_ # !shift0 & shift1 & adder_right2_ & !shift2 # !shift0 & shift1 & shift2 & adder_left1_ # !shift0 & !shift1 & shift2 & adder_right1_ ;Imported pterms FB2_15 # shift0 & !shift1 & shift2 & tt_ls_in # carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & a_/a__D2 ;Imported pterms FB2_17 # carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & !a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & !a_/a__D2; mb.CLK = mb_load; // GCK !pc.D = !mb & and_enable # !shift0 & shift1 & adder_right2_ & !shift2 # !shift0 & shift1 & shift2 & adder_left1_ # !shift0 & !shift1 & shift2 & adder_right1_ ;Imported pterms FB2_1 # shift0 & !shift1 & shift2 & tt_ls_in # shift0 & !shift1 & !shift2 & adder_left2_ # carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & a_/a__D2 ;Imported pterms FB2_3 # carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & !a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & _n0012/_n0012_D2 & !a_/a__D2 # !carry_in_ & !shift0 & !shift1 & !shift2 & !_n0012/_n0012_D2 & a_/a__D2; pc.CLK = pc_load; ****************************** Device Pin Out ***************************** Device : XC9536XL-5-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9536XL-5-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 and_enable 23 GND 2 b_src0 24 b_src2 3 input_bus 25 tt_ls_in 4 carry_out_ 26 mb 5 ac_load 27 adder_right2_ 6 ma_load 28 adder_right1_ 7 mb_load 29 a_src2 8 shift1 30 TDO 9 sc 31 GND 10 GND 32 VCC 11 sr 33 ma 12 KPR 34 a_src1 13 shift2 35 data 14 adder_ 36 b_src1 15 TDI 37 a_src0 16 TMS 38 ac 17 TCK 39 carry_in_ 18 shift0 40 adder_left1_ 19 pc_load 41 VCC 20 mq 42 adder_left2_ 21 VCC 43 data_addr 22 mem 44 pc Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536xl-5-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25