cpldfit: version H.38 Xilinx Inc. Fitter Report Design Name: pdp8 Date: 5-13-2011, 11:38AM Device Used: XC9536XL-5-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 12 /36 ( 33%) 20 /180 ( 11%) 22 /108 ( 20%) 12 /36 ( 33%) 13 /34 ( 38%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 6/18 7/54 7/90 6/17 FB2 6/18 15/54 13/90 6/17 ----- ----- ----- ----- 12/36 22/108 20/180 12/34 * - Resource is exhausted ** Global Control Resources ** Signal 'clock' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 7 7 | I/O : 16 28 Output : 12 12 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 20 20 ** Power Data ** There are 12 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 12 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State break 1 5 FB1_2 3 I/O O STD FAST RESET fetch 1 5 FB1_4 4 I/O O STD FAST RESET intr 1 5 FB1_8 9 I/O O STD FAST RESET ts2 1 4 FB1_11 13 I/O O STD FAST RESET ts3 1 4 FB1_15 20 I/O O STD FAST RESET ts4 2 5 FB1_17 24 I/O O STD FAST RESET exec 3 9 FB2_4 43 I/O O STD FAST RESET defer 2 8 FB2_8 37 I/O O STD FAST RESET ir0 1 6 FB2_10 35 I/O O STD FAST RESET ir1 1 6 FB2_12 33 I/O O STD FAST RESET ir2 1 6 FB2_14 28 I/O O STD FAST RESET ts1 5 11 FB2_17 25 I/O O STD FAST RESET ** 8 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use clock FB1_3 5~ GCK/I/O GCK mb2 FB2_3 42 GTS/I/O I mb1 FB2_5 40 GTS/I/O I intrq FB2_6 39 GSR/I/O I halt FB2_7 38 I/O I brkrq FB2_9 36 I/O I mb0 FB2_13 29 I/O I mb3 FB2_15 27 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 7/47 Number of signals used by logic mapping into function block: 7 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 2 I/O break 1 0 0 4 FB1_2 3 I/O O (unused) 0 0 0 5 FB1_3 5 GCK/I/O GCK fetch 1 0 0 4 FB1_4 4 I/O O (unused) 0 0 0 5 FB1_5 6 GCK/I/O (unused) 0 0 0 5 FB1_6 8 I/O (unused) 0 0 0 5 FB1_7 7 GCK/I/O intr 1 0 0 4 FB1_8 9 I/O O (unused) 0 0 0 5 FB1_9 11 I/O (unused) 0 0 0 5 FB1_10 12 I/O ts2 1 0 0 4 FB1_11 13 I/O O (unused) 0 0 0 5 FB1_12 14 I/O (unused) 0 0 0 5 FB1_13 18 I/O (unused) 0 0 0 5 FB1_14 19 I/O ts3 1 0 0 4 FB1_15 20 I/O O (unused) 0 0 0 5 FB1_16 22 I/O ts4 2 0 0 3 FB1_17 24 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: brkrq 4: ts1 6: ts3 2: halt 5: ts2 7: ts4 3: intrq Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs break X..XXXX................................. 5 fetch .X.XXXX................................. 5 intr ..XXXXX................................. 5 ts2 ...XXXX................................. 4 ts3 ...XXXX................................. 4 ts4 .X.XXXX................................. 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 1 I/O (unused) 0 0 0 5 FB2_2 44 I/O (unused) 0 0 0 5 FB2_3 42 GTS/I/O I exec 3 0 0 2 FB2_4 43 I/O O (unused) 0 0 0 5 FB2_5 40 GTS/I/O I (unused) 0 0 0 5 FB2_6 39 GSR/I/O I (unused) 0 0 0 5 FB2_7 38 I/O I defer 2 0 0 3 FB2_8 37 I/O O (unused) 0 0 0 5 FB2_9 36 I/O I ir0 1 0 0 4 FB2_10 35 I/O O (unused) 0 0 0 5 FB2_11 34 I/O ir1 1 0 0 4 FB2_12 33 I/O O (unused) 0 0 0 5 FB2_13 29 I/O I ir2 1 0 0 4 FB2_14 28 I/O O (unused) 0 0 0 5 FB2_15 27 I/O I (unused) 0 0 0 5 FB2_16 26 I/O ts1 5 0 0 0 FB2_17 25 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: brkrq 6: ir0 11: mb3 2: defer 7: ir1 12: ts1 3: fetch 8: mb0 13: ts2 4: halt 9: mb1 14: ts3 5: intrq 10: mb2 15: ts4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs exec .XX..XX...XXXXX......................... 9 defer ..X..XX...XXXXX......................... 8 ir0 ..X....X...XXXX......................... 6 ir1 ..X.....X..XXXX......................... 6 ir2 ..X......X.XXXX......................... 6 ts1 XXXXXXX....XXXX......................... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** break.D = !ts3 & ts4 & !ts1 & !ts2 & brkrq; break.CLK = clock; // GCK defer.D = mb3 & !ts3 & ts4 & !ts1 & !ts2 & fetch & !ir0 # mb3 & !ts3 & ts4 & !ts1 & !ts2 & fetch & !ir1; defer.CLK = clock; // GCK exec.D = !ts3 & ts4 & !ts1 & !ts2 & defer # !mb3 & !ts3 & ts4 & !ts1 & !ts2 & fetch & !ir0 # !mb3 & !ts3 & ts4 & !ts1 & !ts2 & fetch & !ir1; exec.CLK = clock; // GCK fetch.D = !ts3 & ts4 & !ts1 & !ts2 & !halt; fetch.CLK = clock; // GCK intr.D = !ts3 & ts4 & !ts1 & !ts2 & intrq; intr.CLK = clock; // GCK ir0.D = mb0 & !ts3 & !ts4 & !ts1 & ts2 & fetch; ir0.CLK = clock; // GCK ir1.D = mb1 & !ts3 & !ts4 & !ts1 & ts2 & fetch; ir1.CLK = clock; // GCK ir2.D = mb2 & !ts3 & !ts4 & !ts1 & ts2 & fetch; ir2.CLK = clock; // GCK !ts1.T = ts3 & !ts1 # !ts4 & !ts1 # !ts1 & ts2 # !ts1 & !fetch & !defer & !brkrq & halt & !intrq # !ts1 & !defer & ir0 & ir1 & !brkrq & halt & !intrq; ts1.CLK = clock; // GCK ts2.D = !ts3 & !ts4 & ts1 & !ts2; ts2.CLK = clock; // GCK ts3.D = !ts3 & !ts4 & !ts1 & ts2; ts3.CLK = clock; // GCK ts4.D = ts3 & !ts4 & !ts1 & !ts2 # !ts3 & ts4 & !ts1 & !ts2 & halt; ts4.CLK = clock; // GCK ****************************** Device Pin Out ***************************** Device : XC9536XL-5-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9536XL-5-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 KPR 23 GND 2 KPR 24 ts4 3 break 25 ts1 4 fetch 26 KPR 5 clock 27 mb3 6 KPR 28 ir2 7 KPR 29 mb0 8 KPR 30 TDO 9 intr 31 GND 10 GND 32 VCC 11 KPR 33 ir1 12 KPR 34 KPR 13 ts2 35 ir0 14 KPR 36 brkrq 15 TDI 37 defer 16 TMS 38 halt 17 TCK 39 intrq 18 KPR 40 mb1 19 KPR 41 VCC 20 ts3 42 mb2 21 VCC 43 exec 22 KPR 44 KPR Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536xl-5-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25