1 TD8E interface v1.0 Anders Sandahl 2019 <b>TANTALUM CAPACITOR</b> >NAME >VALUE <b>ELECTROLYTIC CAPACITOR</b><p> grid 22.86 mm, diameter 9 mm >NAME >VALUE <b>RESISTOR</b><p> chip >NAME >VALUE <b>RESISTOR</b><p> chip >NAME >VALUE >NAME >VALUE <b>POTENTIOMETER</b> >NAME >VALUE 1 3 2 3 1 <B>DIODE</B> >NAME >VALUE <b>SOT-23</b> >NAME >VALUE <b>Diode</b> >NAME >VALUE <b>SOIC-8</b> CASE 751-07<p> Source: http://www.onsemi.com/pub/Collateral/MC34164-D.PDF<p> <b>D (R-PDSO-G8)</b>PLATIC SMALL-OUTLINE PACKAGE<br> Source: http://focus.ti.com/lit/ds/symlink/tlc27l2.pdf >NAME >VALUE <b>Small Outline Transistor 223</b><p> PLASTIC PACKAGE CASE 318E-04<br> Source: http://www.onsemi.co.jp .. LM137M-D.PDF >NAME >VALUE <b>Small Outline Transistor 223</b><p> PLASTIC PACKAGE CASE 318E-04<br> Source: http://www.onsemi.co.jp .. LM137M-D.PDF >NAME >VALUE <b>Small Outline Transistor 223</b><p> PLASTIC PACKAGE CASE 318E-04<br> Source: http://www.onsemi.co.jp .. LM137M-D.PDF >NAME >VALUE <b>Small Outline Transistor 223</b><p> PLASTIC PACKAGE CASE 318E-04<br> Source: http://www.onsemi.co.jp .. LM137M-D.PDF >NAME >VALUE direction of pcb transportation for wavesoldering >NAME >VALUE >NAME >VALUE >VALUE >NAME <b>Small Outline package</b> 150 mil >VALUE >NAME <b>EAGLE Design Rules</b> <p> The default Design Rules have been set to cover a wide range of applications. Your particular design may have different requirements, so please make the necessary adjustments and save your customized design rules under a new name.