# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:40:57 March 29, 2023 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # BM8L_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY MAX7000S set_global_assignment -name DEVICE "EPM7128SQC160-15" set_global_assignment -name TOP_LEVEL_ENTITY bm8l set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:40:57 MARCH 29, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name VERILOG_FILE BM8L.v set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files