Atmel ATF1504AS Fitter Version 1.8.7.8 ,running Sun Dec 09 17:09:19 2018 fit1504 C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.tt2 -CUPL -dev P1504C84 -JTAG ON ****** Initial fitting strategy and property ****** Pla_in_file = M220A.tt2 Pla_out_file = M220A.tt3 Jedec_file = M220A.jed Vector_file = M220A.tmv verilog_file = M220A.vt Time_file = Log_file = M220A.fit err_file = Device_name = PLCC84 Module_name = Package_type = PLCC Preassign_file = Property_file = Sleep_mode = Preassignment = Security_mode = OFF Pin_keep_mode = ON Dedicated_input_clock = Dedicated_input_reset = Dedicated_input_oe = supporter = CUPL optimize = ON Soft_buffer = Xor_synthesis = OFF Foldback_logic = on Expander = Cascade_logic = OFF Dedicated_input = Output_fast = OFF ******************************* Power down pin 1 = OFF Power down pin 2 = OFF power_reset = OFF JTAG = ON TDI pullup = OFF TMS pullup = OFF MC_power = OFF Open_collector = OFF ITD0 = ON ITD1 = ON ITD2 = ON Fast_inlatch = off ******************************* Info: C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A uses 95% of the pins available in device PLCC84 If you wish to have more pins available for future logic changes Atmel recommends using a larger device --------------------------------------------------------- Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF ... ## Warning : Placement fail --------------------------------------------------------- Fitter_Pass 2, Preassign = KEEP, CASCADE_LOGIC : (TRY) ... Performing global Output Enable pin assignments ... Performing global pin assignments ... -------------------------------------- Final global control pins assignment (if applicable)... ------------------------------------------------------- Performing input pin pre-assignments ... ------------------------------------ and_h assigned to pin 2 shift_r1 assigned to pin 83 adder0 assigned to pin 1 adder1 assigned to pin 84 Attempt to place floating signals ... ------------------------------------ data2 is placed at pin 22 (MC 1) io3 is placed at pin 21 (MC 2) mq3_h is placed at pin 20 (MC 3) sc3 is placed at pin 18 (MC 4) data3 is placed at pin 17 (MC 5) ma_enabl is placed at pin 16 (MC 6) br2 is placed at pin 15 (MC 7) TDI is placed at pin 14 (MC 8) mem2 is placed at pin 12 (MC 9) pc_enabl is placed at pin 11 (MC 10) da2 is placed at pin 10 (MC 11) da_enabl is placed at pin 9 (MC 12) mem_enabl is placed at pin 8 (MC 13) bu1 is placed at pin 6 (MC 14) XXL_110 is placed at feedback node 614 (MC 14) bv2 is placed at pin 5 (MC 15) XXL_105 is placed at feedback node 615 (MC 15) bv1 is placed at pin 4 (MC 16) XXL_106 is placed at feedback node 616 (MC 16) sr_enabl is placed at pin 41 (MC 17) sr3 is placed at pin 40 (MC 18) sc2 is placed at pin 39 (MC 19) be2 is placed at pin 37 (MC 20) sr2 is placed at pin 36 (MC 21) sc_enabl is placed at pin 35 (MC 22) mq_enabl is placed at pin 34 (MC 23) ac_enabl is placed at pin 33 (MC 24) mq2_h is placed at pin 31 (MC 25) ac_low_enabl is placed at pin 30 (MC 26) c0 is placed at pin 29 (MC 27) n_t_12x is placed at feedback node 627 (MC 27) c2 is placed at pin 28 (MC 28) io2 is placed at pin 27 (MC 29) XXL_111 is placed at feedback node 629 (MC 29) io_enabl is placed at pin 25 (MC 30) XXL_109 is placed at feedback node 630 (MC 30) data_enabl is placed at pin 24 (MC 31) XXL_107 is placed at feedback node 631 (MC 31) TMS is placed at pin 23 (MC 32) XXL_108 is placed at feedback node 632 (MC 32) ac2_l is placed at pin 44 (MC 33) ac2_h is placed at pin 45 (MC 34) ac3_h is placed at pin 46 (MC 35) ac3_l is placed at pin 48 (MC 36) au1 is placed at pin 49 (MC 37) au2 is placed at pin 50 (MC 38) at2 is placed at pin 51 (MC 39) as1 is placed at pin 52 (MC 40) as2 is placed at pin 54 (MC 41) ar1 is placed at pin 55 (MC 42) n_t_5x is placed at feedback node 642 (MC 42) pc2_l is placed at pin 56 (MC 43) pc2_h is placed at pin 57 (MC 44) pc3_l is placed at pin 58 (MC 45) pc3_h is placed at pin 60 (MC 46) an2 is placed at pin 61 (MC 47) n_t_8x is placed at feedback node 647 (MC 47) TCK is placed at pin 62 (MC 48) n_t_14x is placed at feedback node 648 (MC 48) ma2_l is placed at pin 63 (MC 49) ma2_h is placed at pin 64 (MC 50) ma3_l is placed at pin 65 (MC 51) ma3_h is placed at pin 67 (MC 52) ak1 is placed at pin 68 (MC 53) ak2 is placed at pin 69 (MC 54) aj1 is placed at pin 70 (MC 55) TDO is placed at pin 71 (MC 56) adder5 is placed at pin 73 (MC 57) shift_l2 is placed at pin 74 (MC 58) adder4 is placed at pin 75 (MC 59) adder3 is placed at pin 76 (MC 60) shift_l1 is placed at pin 77 (MC 61) no_shift is placed at pin 79 (MC 62) adder2 is placed at pin 80 (MC 63) shift_r2 is placed at pin 81 (MC 64) m p d e s s n s c a m h h o h _ _ _ aa i i a _ i a a e e e a dd f f d s f d d n n n n dd t t d h t d d a d a a G b b b V d ee _ G _ e i V _ e e b a b b N u v v C _ rr r N r r f C l r r l 2 l l D 1 2 1 C h 01 1 D 2 2 t C 1 3 4 ------------------------------------------- / 11 9 7 5 3 1 83 81 79 77 75 \ / 10 8 6 4 2 84 82 80 78 76 \ mem2 | 12 (*) 74 | shift_l2 VCC | 13 73 | adder5 TDI | 14 72 | GND br2 | 15 71 | TDO ma_enabl | 16 70 | aj1 data3 | 17 69 | ak2 sc3 | 18 68 | ak1 GND | 19 67 | ma3_h mq3_h | 20 66 | VCC io3 | 21 65 | ma3_l data2 | 22 ATF1504 64 | ma2_h TMS | 23 84-Lead PLCC 63 | ma2_l data_enabl | 24 62 | TCK io_enabl | 25 61 | an2 VCC | 26 60 | pc3_h io2 | 27 59 | GND c2 | 28 58 | pc3_l c0 | 29 57 | pc2_h ac_low_enabl | 30 56 | pc2_l mq2_h | 31 55 | ar1 GND | 32 54 | as2 \ 34 36 38 40 42 44 46 48 50 52 / \ 33 35 37 39 41 43 45 47 49 51 53/ -------------------------------------------- a m s s b V s s s G V a a a G a a a a a V c q c r e C c r r N C c c c N c u u t s C _ _ _ 2 2 C 2 3 _ D C 2 2 3 D 3 1 2 2 1 C e e e e _ _ _ _ n n n n l h h l a a a a b b b b l l l l VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V) GND = GND pin which must be connected to ground TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface NC = Unused I/O pins which must be unconnected on the board Universal-Interconnect-Multiplexer assignments ------------------------------------------------ FanIn assignment for block A [25] { adder3,adder4,adder1,adder2,ac3_h,ac_low_enabl,ac2_h,adder0, io2,io_enabl,io3, mq3_h,mq_enabl,mq2_h, no_shift, sr2,shift_l2,sc_enabl,sc3,shift_r2,sr_enabl,sc2,sr3,shift_l1,shift_r1, } Multiplexer assignment for block A adder3 (MC3 P) : MUX 0 Ref (D60p) io2 (MC21 P) : MUX 2 Ref (B29p) io_enabl (MC13 P) : MUX 4 Ref (B30p) sr2 (MC24 P) : MUX 5 Ref (B21p) shift_l2 (MC8 P) : MUX 6 Ref (D58p) mq3_h (MC14 P) : MUX 7 Ref (A3p) mq_enabl (MC15 P) : MUX 11 Ref (B23p) sc_enabl (MC17 P) : MUX 13 Ref (B22p) adder4 (MC7 P) : MUX 14 Ref (D59p) io3 (MC12 P) : MUX 15 Ref (A2p) sc3 (MC16 P) : MUX 17 Ref (A4p) adder1 (MC9 FB) : MUX 19 Ref (OE1) shift_r2 (MC11 P) : MUX 20 Ref (D64p) sr_enabl (MC19 P) : MUX 21 Ref (B17p) sc2 (MC23 P) : MUX 23 Ref (B19p) adder2 (MC4 P) : MUX 24 Ref (D63p) ac3_h (MC2 P) : MUX 25 Ref (C35p) ac_low_enabl (MC20 P) : MUX 26 Ref (B26p) sr3 (MC18 P) : MUX 27 Ref (B18p) shift_l1 (MC6 P) : MUX 28 Ref (D61p) ac2_h (MC1 P) : MUX 29 Ref (C34p) no_shift (MC5 P) : MUX 30 Ref (D62p) shift_r1 (MC10 FB) : MUX 33 Ref (GCLK) mq2_h (MC22 P) : MUX 34 Ref (B25p) adder0 (MC25 FB) : MUX 36 Ref (GCLR) FanIn assignment for block B [24] { XXL_109, adder3,adder4,adder5,adder1,adder2, c0, da2,da_enabl, ma2_h,mem2,mem_enabl,ma_enabl, n_t_8x,n_t_14x,n_t_12x,no_shift,n_t_5x, pc_enabl,pc2_h, shift_l2,shift_r2,shift_l1,shift_r1, } Multiplexer assignment for block B da2 (MC24 P) : MUX 0 Ref (A11p) adder3 (MC8 P) : MUX 2 Ref (D60p) n_t_8x (MC5 FB) : MUX 3 Ref (C47fb) adder4 (MC12 P) : MUX 4 Ref (D59p) shift_l2 (MC13 P) : MUX 6 Ref (D58p) ma2_h (MC7 P) : MUX 7 Ref (D50p) pc_enabl (MC18 P) : MUX 8 Ref (A10p) da_enabl (MC19 P) : MUX 10 Ref (A12p) XXL_109 (MC2 FB) : MUX 11 Ref (B30fb) mem2 (MC22 P) : MUX 12 Ref (A9p) n_t_14x (MC6 FB) : MUX 15 Ref (C48fb) adder5 (MC20 P) : MUX 16 Ref (D57p) adder1 (MC14 FB) : MUX 19 Ref (OE1) mem_enabl (MC23 P) : MUX 20 Ref (A13p) shift_r2 (MC16 P) : MUX 22 Ref (D64p) n_t_12x (MC1 FB) : MUX 23 Ref (B27fb) pc2_h (MC4 P) : MUX 24 Ref (C44p) ma_enabl (MC21 P) : MUX 25 Ref (A6p) no_shift (MC10 P) : MUX 26 Ref (D62p) c0 (MC17 P) : MUX 28 Ref (B27p) n_t_5x (MC3 FB) : MUX 33 Ref (C42fb) adder2 (MC9 P) : MUX 34 Ref (D63p) shift_l1 (MC11 P) : MUX 36 Ref (D61p) shift_r1 (MC15 FB) : MUX 39 Ref (GCLK) FanIn assignment for block C [25] { XXL_106,XXL_105, at2,an2,ac_enabl,au1,ar1,ac3_h,ak2,ac2_h,aj1,as2, bv2,bv1,br2,bu1,be2, data2,data_enabl,da_enabl,data3, ma3_h, pc3_h,pc_enabl,pc2_h, } Multiplexer assignment for block C ma3_h (MC9 P) : MUX 1 Ref (D52p) pc3_h (MC8 P) : MUX 2 Ref (C46p) data2 (MC25 P) : MUX 3 Ref (A1p) at2 (MC5 P) : MUX 5 Ref (C39p) an2 (MC16 P) : MUX 6 Ref (C47p) data_enabl (MC24 P) : MUX 8 Ref (B31p) da_enabl (MC13 P) : MUX 10 Ref (A12p) pc_enabl (MC12 P) : MUX 12 Ref (A10p) ac_enabl (MC21 P) : MUX 13 Ref (B24p) au1 (MC14 P) : MUX 17 Ref (C37p) bv2 (MC20 P) : MUX 20 Ref (A15p) data3 (MC23 P) : MUX 21 Ref (A5p) ar1 (MC15 P) : MUX 22 Ref (C42p) pc2_h (MC7 P) : MUX 24 Ref (C44p) ac3_h (MC4 P) : MUX 25 Ref (C35p) ak2 (MC10 P) : MUX 27 Ref (D54p) ac2_h (MC3 P) : MUX 29 Ref (C34p) bv1 (MC19 P) : MUX 30 Ref (A16p) br2 (MC18 P) : MUX 31 Ref (A7p) bu1 (MC17 P) : MUX 32 Ref (A14p) aj1 (MC11 P) : MUX 33 Ref (D55p) as2 (MC6 P) : MUX 34 Ref (C41p) be2 (MC22 P) : MUX 35 Ref (B20p) XXL_106 (MC2 FB) : MUX 37 Ref (A16fb) XXL_105 (MC1 FB) : MUX 39 Ref (A15fb) FanIn assignment for block D [17] { XXL_111,XXL_108,XXL_107,XXL_110, at2,and_h,ak2,ak1,as2,aj1, c0, ma2_h,ma3_h, n_t_8x,n_t_14x,n_t_12x,n_t_5x, } Multiplexer assignment for block D ma2_h (MC11 P) : MUX 1 Ref (D50p) at2 (MC6 P) : MUX 5 Ref (C39p) n_t_8x (MC9 FB) : MUX 7 Ref (C47fb) n_t_14x (MC10 FB) : MUX 9 Ref (C48fb) XXL_111 (MC3 FB) : MUX 11 Ref (B29fb) and_h (MC16 FB) : MUX 12 Ref (OE2) ma3_h (MC12 P) : MUX 13 Ref (D52p) XXL_108 (MC5 FB) : MUX 17 Ref (B32fb) XXL_107 (MC4 FB) : MUX 19 Ref (B31fb) c0 (MC15 P) : MUX 20 Ref (B27p) ak2 (MC13 P) : MUX 21 Ref (D54p) n_t_12x (MC2 FB) : MUX 23 Ref (B27fb) n_t_5x (MC8 FB) : MUX 25 Ref (C42fb) XXL_110 (MC1 FB) : MUX 29 Ref (A14fb) ak1 (MC17 P) : MUX 31 Ref (D53p) as2 (MC7 P) : MUX 32 Ref (C41p) aj1 (MC14 P) : MUX 33 Ref (D55p) Creating JEDEC file C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.jed ... PLCC84 programmed logic: ----------------------------------- ac3_l = !ac3_h.Q; ac2_l = !ac2_h.Q; au2 = !at2.Q; as1 = !as2.Q; ma2_l = !ma2_h.Q; ma3_l = !ma3_h.Q; n_t_12x = ((ma2_h.Q & ma_enabl) # (mem2 & mem_enabl) # (pc2_h.Q & pc_enabl) # (da2 & da_enabl)); n_t_14x = ((bu1 & da_enabl) # (br2 & ma3_h.Q) # (pc3_h.Q & pc_enabl) # (bv1 & bv2)); pc2_l = !pc2_h.Q; pc3_l = !pc3_h.Q; n_t_5x = ((ac2_h.Q & ac_enabl) # (data2 & data_enabl) # XXL_105); n_t_8x = ((ac3_h.Q & ac_enabl) # be2 # (data3 & data_enabl) # XXL_106); !adder2 = ((!c0 & n_t_12x & n_t_5x & n_t_8x) # (n_t_12x & n_t_14x & n_t_5x & n_t_8x) # XXL_107 # XXL_108); adder3 = ((c0 & !n_t_14x & !n_t_8x) # (!c0 & !n_t_14x & n_t_8x) # (!c0 & n_t_14x & !n_t_8x) # (c0 & n_t_14x & n_t_8x)); c2 = ((!n_t_8x & c0 & !n_t_12x) # (!n_t_14x & c0 & !n_t_12x) # XXL_109); !aj1 = ((and_h & !at2.Q) # XXL_110); !ak2 = ((and_h & !as2.Q) # XXL_111); ac2_h.D = aj1; ac3_h.D = ak2; ma2_h.D = aj1; as2.D = ak2; ma3_h.D = ak2; at2.D = aj1; pc2_h.D = aj1; pc3_h.D = ak2; XXL_105 = ((io2 & io_enabl) # (mq2_h & mq_enabl) # (sc2 & sc_enabl) # (sr2 & sr_enabl) # (!ac2_h.Q & ac_low_enabl)); XXL_106 = ((io3 & io_enabl) # (mq3_h & mq_enabl) # (sc3 & sc_enabl) # (sr3 & sr_enabl) # (!ac3_h.Q & ac_low_enabl)); XXL_107 = ((c0 & n_t_12x & !n_t_14x & !n_t_5x) # (!c0 & !n_t_12x & n_t_14x & !n_t_5x) # (c0 & !n_t_12x & !n_t_14x & n_t_5x) # (!c0 & n_t_12x & n_t_14x & n_t_5x) # (c0 & n_t_12x & !n_t_5x & !n_t_8x)); XXL_108 = ((n_t_12x & !n_t_14x & !n_t_5x & !n_t_8x) # (c0 & !n_t_12x & n_t_5x & !n_t_8x) # (!n_t_12x & !n_t_14x & n_t_5x & !n_t_8x) # (!c0 & !n_t_12x & !n_t_5x & n_t_8x) # (!n_t_12x & n_t_14x & !n_t_5x & n_t_8x)); XXL_109 = ((!n_t_14x & !n_t_5x & c0) # (!n_t_5x & !n_t_12x) # (!n_t_14x & !n_t_5x & !n_t_8x) # (!n_t_14x & !n_t_8x & !n_t_12x) # (!n_t_5x & !n_t_8x & c0)); XXL_110 = ((adder2 & no_shift) # (adder3 & shift_l1) # (adder4 & shift_l2) # (adder1 & shift_r1) # (adder0 & shift_r2)); XXL_111 = ((adder3 & no_shift) # (adder4 & shift_l1) # (adder5 & shift_l2) # (adder2 & shift_r1) # (adder1 & shift_r2)); ac2_h.C = au1; ac3_h.C = au1; ma2_h.C = ak1; as2.C = ar1; ma3_h.C = ak1; at2.C = ar1; pc2_h.C = an2; pc3_h.C = an2; PLCC84 Pin/Node Placement: ------------------------------------ Pin 1 = adder0; Pin 2 = and_h; Pin 4 = bv1; /* MC 16 */ Pin 5 = bv2; /* MC 15 */ Pin 6 = bu1; /* MC 14 */ Pin 8 = mem_enabl; /* MC 13 */ Pin 9 = da_enabl; /* MC 12 */ Pin 10 = da2; /* MC 11 */ Pin 11 = pc_enabl; /* MC 10 */ Pin 12 = mem2; /* MC 9 */ Pin 14 = TDI; /* MC 8 */ Pin 15 = br2; /* MC 7 */ Pin 16 = ma_enabl; /* MC 6 */ Pin 17 = data3; /* MC 5 */ Pin 18 = sc3; /* MC 4 */ Pin 20 = mq3_h; /* MC 3 */ Pin 21 = io3; /* MC 2 */ Pin 22 = data2; /* MC 1 */ Pin 23 = TMS; /* MC 32 */ Pin 24 = data_enabl; /* MC 31 */ Pin 25 = io_enabl; /* MC 30 */ Pin 27 = io2; /* MC 29 */ Pin 28 = c2; /* MC 28 */ Pin 29 = c0; /* MC 27 */ Pin 30 = ac_low_enabl; /* MC 26 */ Pin 31 = mq2_h; /* MC 25 */ Pin 33 = ac_enabl; /* MC 24 */ Pin 34 = mq_enabl; /* MC 23 */ Pin 35 = sc_enabl; /* MC 22 */ Pin 36 = sr2; /* MC 21 */ Pin 37 = be2; /* MC 20 */ Pin 39 = sc2; /* MC 19 */ Pin 40 = sr3; /* MC 18 */ Pin 41 = sr_enabl; /* MC 17 */ Pin 44 = ac2_l; /* MC 33 */ Pin 45 = ac2_h; /* MC 34 */ Pin 46 = ac3_h; /* MC 35 */ Pin 48 = ac3_l; /* MC 36 */ Pin 49 = au1; /* MC 37 */ Pin 50 = au2; /* MC 38 */ Pin 51 = at2; /* MC 39 */ Pin 52 = as1; /* MC 40 */ Pin 54 = as2; /* MC 41 */ Pin 55 = ar1; /* MC 42 */ Pin 56 = pc2_l; /* MC 43 */ Pin 57 = pc2_h; /* MC 44 */ Pin 58 = pc3_l; /* MC 45 */ Pin 60 = pc3_h; /* MC 46 */ Pin 61 = an2; /* MC 47 */ Pin 62 = TCK; /* MC 48 */ Pin 63 = ma2_l; /* MC 49 */ Pin 64 = ma2_h; /* MC 50 */ Pin 65 = ma3_l; /* MC 51 */ Pin 67 = ma3_h; /* MC 52 */ Pin 68 = ak1; /* MC 53 */ Pin 69 = ak2; /* MC 54 */ Pin 70 = aj1; /* MC 55 */ Pin 71 = TDO; /* MC 56 */ Pin 73 = adder5; /* MC 57 */ Pin 74 = shift_l2; /* MC 58 */ Pin 75 = adder4; /* MC 59 */ Pin 76 = adder3; /* MC 60 */ Pin 77 = shift_l1; /* MC 61 */ Pin 79 = no_shift; /* MC 62 */ Pin 80 = adder2; /* MC 63 */ Pin 81 = shift_r2; /* MC 64 */ Pin 83 = shift_r1; Pin 84 = adder1; PINNODE 614 = XXL_110; /* MC 14 Feedback */ PINNODE 615 = XXL_105; /* MC 15 Feedback */ PINNODE 616 = XXL_106; /* MC 16 Feedback */ PINNODE 627 = n_t_12x; /* MC 27 Feedback */ PINNODE 629 = XXL_111; /* MC 29 Feedback */ PINNODE 630 = XXL_109; /* MC 30 Feedback */ PINNODE 631 = XXL_107; /* MC 31 Feedback */ PINNODE 632 = XXL_108; /* MC 32 Feedback */ PINNODE 642 = n_t_5x; /* MC 42 Feedback */ PINNODE 647 = n_t_8x; /* MC 47 Feedback */ PINNODE 648 = n_t_14x; /* MC 48 Feedback */ ** Resource Usage ** DCERP Field = Summary of Allocations. ||||| |||||_Preset [p,-] == p = PT preset, - No Preset. |||| ||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset. ||| |||___Clock Enable [e,-] == e = Product Term, - always enabled, - none. || ||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock. | |_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff. For input only = INPUT. MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT output_slew MC1 22 -- data2 INPUT -- -- -- 0 slow MC2 21 -- io3 INPUT -- -- -- 0 slow MC3 20 -- mq3_h INPUT -- -- -- 0 slow MC4 18 -- sc3 INPUT -- -- -- 0 slow MC5 17 -- data3 INPUT -- -- -- 0 slow MC6 16 -- ma_enabl INPUT -- -- -- 0 slow MC7 15 -- br2 INPUT -- -- -- 0 slow MC8 14 -- TDI INPUT -- -- -- 0 slow MC9 12 -- mem2 INPUT -- -- -- 0 slow MC10 11 -- pc_enabl INPUT -- -- -- 0 slow MC11 10 -- da2 INPUT -- -- -- 0 slow MC12 9 -- da_enabl INPUT -- -- -- 0 slow MC13 8 -- mem_enabl INPUT -- -- -- 0 slow MC14 6 -- bu1 INPUT XXL_110 C---- NA -- 5 slow MC15 5 -- bv2 INPUT XXL_105 C---- NA -- 5 slow MC16 4 -- bv1 INPUT XXL_106 C---- NA -- 5 slow MC17 41 -- sr_enabl INPUT -- -- -- 0 slow MC18 40 -- sr3 INPUT -- -- -- 0 slow MC19 39 -- sc2 INPUT -- -- -- 0 slow MC20 37 -- be2 INPUT -- -- -- 0 slow MC21 36 -- sr2 INPUT -- -- -- 0 slow MC22 35 -- sc_enabl INPUT -- -- -- 0 slow MC23 34 -- mq_enabl INPUT -- -- -- 0 slow MC24 33 -- ac_enabl INPUT -- -- -- 0 slow MC25 31 -- mq2_h INPUT -- -- -- 0 slow MC26 30 -- ac_low_enabl INPUT -- -- -- 0 slow MC27 29 -- c0 INPUT n_t_12x C---- -- -- 4 slow MC28 28 on c2 C---- -- -- -- 3 slow MC29 27 -- io2 INPUT XXL_111 C---- NA -- 5 slow MC30 25 -- io_enabl INPUT XXL_109 C---- NA -- 5 slow MC31 24 -- data_enabl INPUT XXL_107 C---- NA -- 5 slow MC32 23 -- TMS INPUT XXL_108 C---- NA -- 5 slow MC33 44 on ac2_l C---- -- -- -- 1 slow MC34 45 on ac2_h Dc--- -- -- -- 2 slow MC35 46 on ac3_h Dc--- -- -- -- 2 slow MC36 48 on ac3_l C---- -- -- -- 1 slow MC37 49 -- au1 INPUT -- -- -- 0 slow MC38 50 on au2 C---- -- -- -- 1 slow MC39 51 on at2 Dc--- -- -- -- 2 slow MC40 52 on as1 C---- -- -- -- 1 slow MC41 54 on as2 Dc--- -- -- -- 2 slow MC42 55 -- ar1 INPUT n_t_5x C---- -- -- 3 slow MC43 56 on pc2_l C---- -- -- -- 1 slow MC44 57 on pc2_h Dc--- -- -- -- 2 slow MC45 58 on pc3_l C---- -- -- -- 1 slow MC46 60 on pc3_h Dc--- -- -- -- 2 slow MC47 61 -- an2 INPUT n_t_8x C---- -- -- 4 slow MC48 62 -- TCK INPUT n_t_14x C---- -- -- 4 slow MC49 63 on ma2_l C---- -- -- -- 1 slow MC50 64 on ma2_h Dc--- -- -- -- 2 slow MC51 65 on ma3_l C---- -- -- -- 1 slow MC52 67 on ma3_h Dc--- -- -- -- 2 slow MC53 68 -- ak1 INPUT -- -- -- 0 slow MC54 69 on ak2 C---- -- -- -- 2 slow MC55 70 on aj1 C---- -- -- -- 2 slow MC56 71 -- TDO INPUT -- -- -- 0 slow MC57 73 -- adder5 INPUT -- -- -- 0 slow MC58 74 -- shift_l2 INPUT -- -- -- 0 slow MC59 75 -- adder4 INPUT -- -- -- 0 slow MC60 76 on adder3 C---- -- -- -- 4 slow MC61 77 -- shift_l1 INPUT -- -- -- 0 slow MC62 79 -- no_shift INPUT -- -- -- 0 slow MC63 80 on adder2 C---- -- -- -- 4 slow MC64 81 -- shift_r2 INPUT -- -- -- 0 slow MC0 2 and_h INPUT -- -- -- 0 slow MC0 1 adder0 INPUT -- -- -- 0 slow MC0 84 adder1 INPUT -- -- -- 0 slow MC0 83 shift_r1 INPUT -- -- -- 0 slow Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades A: LC1 - LC16 3/16(18%) 16/16(100%) 0/16(0%) 15/80(18%) (25) 0 B: LC17 - LC32 6/16(37%) 16/16(100%) 0/16(0%) 27/80(33%) (24) 0 C: LC33 - LC48 15/16(93%) 16/16(100%) 0/16(0%) 29/80(36%) (25) 0 D: LC49 - LC64 8/16(50%) 16/16(100%) 0/16(0%) 18/80(22%) (17) 0 Total dedicated input used: 4/4 (100%) Total I/O pins used 64/64 (100%) Total Logic cells used 32/64 (50%) Total Flip-Flop used 8/64 (12%) Total Foldback logic used 0/64 (0%) Total Nodes+FB/MCells 32/64 (50%) Total cascade used 0 Total input pins 47 Total output pins 21 Total Pts 89 Creating pla file C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M220\ATMEL\M220A.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms... ---------------- End fitter, Design FITS $Device PLCC84 fits FIT1504 completed in 0.00 seconds