Atmel ATF1508AS Fitter Version 1.8.7.8 ,running Thu May 03 23:11:21 2018 fit1508 C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M8416\TOPLD\SN74189.tt2 -CUPL -dev P1508T100 -JTAG ON ****** Initial fitting strategy and property ****** Pla_in_file = SN74189.tt2 Pla_out_file = SN74189.tt3 Jedec_file = SN74189.jed Vector_file = SN74189.tmv verilog_file = SN74189.vt Time_file = Log_file = SN74189.fit err_file = Device_name = TQFP100 Module_name = Package_type = TQFP Preassign_file = Property_file = Sleep_mode = Preassignment = Security_mode = OFF Pin_keep_mode = ON Dedicated_input_clock = Dedicated_input_reset = Dedicated_input_oe = supporter = CUPL optimize = ON Soft_buffer = Xor_synthesis = OFF Foldback_logic = on Expander = Cascade_logic = OFF Dedicated_input = Output_fast = OFF ******************************* Power down pin 1 = OFF Power down pin 2 = OFF power_reset = OFF JTAG = ON TDI pullup = OFF TMS pullup = OFF MC_power = OFF Open_collector = OFF ITD0 = ON ITD1 = ON ITD2 = ON Fast_inlatch = off ******************************* --------------------------------------------------------- Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF ... ## ERROR : Bad user pin assignement : 101 ## ERROR : Bad user pin assignement --------------------------------------------------------- Fitter_Pass 2, Preassign = KEEP, NODE ASSIGN : OFF ... Performing global Output Enable pin assignments ... Performing global pin assignments ... -------------------------------------- Final global control pins assignment (if applicable)... ------------------------------------------------------- Performing input pin pre-assignments ... ------------------------------------ Attempt to place floating signals ... ------------------------------------ rd2 is placed at feedback node 601 (MC 1) rb1 is placed at feedback node 602 (MC 2) rd1 is placed at feedback node 603 (MC 3) rb2 is placed at feedback node 604 (MC 4) rd3 is placed at feedback node 605 (MC 5) rc3 is placed at feedback node 606 (MC 6) ra3 is placed at feedback node 607 (MC 7) rc1 is placed at feedback node 608 (MC 8) rc2 is placed at feedback node 609 (MC 9) ra1 is placed at feedback node 610 (MC 10) rb3 is placed at feedback node 611 (MC 11) ra2 is placed at feedback node 612 (MC 12) A0 is placed at pin 94 (MC 13) A1 is placed at pin 93 (MC 14) d2 is placed at pin 92 (MC 16) rg2 is placed at feedback node 617 (MC 17) re2 is placed at feedback node 618 (MC 18) rf4 is placed at feedback node 619 (MC 19) rd4 is placed at feedback node 620 (MC 20) rg1 is placed at feedback node 621 (MC 21) rf2 is placed at feedback node 622 (MC 22) re1 is placed at feedback node 623 (MC 23) re4 is placed at feedback node 624 (MC 24) rf1 is placed at feedback node 625 (MC 25) rc4 is placed at feedback node 626 (MC 26) A2 is placed at pin 7 (MC 27) A3 is placed at pin 6 (MC 29) d1 is placed at pin 5 (MC 30) ra4 is placed at feedback node 631 (MC 31) TDI is placed at pin 4 (MC 32) rb4 is placed at feedback node 632 (MC 32) rj3 is placed at feedback node 633 (MC 33) rh4 is placed at feedback node 634 (MC 34) ri4 is placed at feedback node 635 (MC 35) rg4 is placed at feedback node 636 (MC 36) rj1 is placed at feedback node 637 (MC 37) ri3 is placed at feedback node 638 (MC 38) rh1 is placed at feedback node 639 (MC 39) rh3 is placed at feedback node 640 (MC 40) ri1 is placed at feedback node 641 (MC 41) rg3 is placed at feedback node 642 (MC 42) CE is placed at pin 19 (MC 43) WE is placed at pin 17 (MC 45) d3 is placed at pin 16 (MC 46) re3 is placed at feedback node 647 (MC 47) TMS is placed at pin 15 (MC 48) rf3 is placed at feedback node 648 (MC 48) rm2 is placed at feedback node 649 (MC 49) rj4 is placed at feedback node 650 (MC 50) rm1 is placed at feedback node 651 (MC 51) rk1 is placed at feedback node 652 (MC 52) rl4 is placed at feedback node 653 (MC 53) rl2 is placed at feedback node 654 (MC 54) rj2 is placed at feedback node 655 (MC 55) rk4 is placed at feedback node 656 (MC 56) rl1 is placed at feedback node 657 (MC 57) rh2 is placed at feedback node 658 (MC 58) rk2 is placed at feedback node 659 (MC 59) ri2 is placed at feedback node 660 (MC 60) I1 is placed at pin 29 (MC 61) I2 is placed at pin 28 (MC 62) d4 is placed at pin 27 (MC 64) rp4 is placed at feedback node 665 (MC 65) rn2 is placed at feedback node 666 (MC 66) rp3 is placed at feedback node 667 (MC 67) rn1 is placed at feedback node 668 (MC 68) rp2 is placed at feedback node 669 (MC 69) rp1 is placed at feedback node 670 (MC 70) rm4 is placed at feedback node 671 (MC 71) ro4 is placed at feedback node 672 (MC 72) ro3 is placed at feedback node 673 (MC 73) rm3 is placed at feedback node 674 (MC 74) ro2 is placed at feedback node 675 (MC 75) rl3 is placed at feedback node 676 (MC 76) ro1 is placed at feedback node 677 (MC 77) rn4 is placed at feedback node 678 (MC 78) rk3 is placed at feedback node 679 (MC 79) rn3 is placed at feedback node 680 (MC 80) I4 is placed at pin 52 (MC 81) I3 is placed at pin 53 (MC 83) TCK is placed at pin 62 (MC 96) TDO is placed at pin 73 (MC 112) G V G V N A A d C N C D 0 1 2 C D C ------------------------------------------------------ / 100 98 96 94 92 90 88 86 84 82 80 78 76 \ / 99 97 95 93 91 89 87 85 83 81 79 77 \ | 1 75 | | 2 74 | GND VCC | 3 73 | TDO TDI | 4 72 | d1 | 5 71 | A3 | 6 70 | A2 | 7 69 | | 8 68 | | 9 67 | | 10 66 | VCC GND | 11 65 | | 12 ATF1508 64 | | 13 100-Lead TQFP 63 | | 14 62 | TCK TMS | 15 61 | d3 | 16 60 | WE | 17 59 | GND VCC | 18 58 | CE | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | I3 | 24 52 | I4 | 25 51 | VCC \ 27 29 31 33 35 37 39 41 43 45 47 49 / \ 26 28 30 32 34 36 38 40 42 44 46 48 50 / ------------------------------------------------------ G d I I V G V G N 4 2 1 C N C N D C D C D VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V) GND = GND pin which must be connected to ground TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface NC = Unused I/O pins which must be unconnected on the board Universal-Interconnect-Multiplexer assignments ------------------------------------------------ FanIn assignment for block A [25] { A0,A2,A1,A3, CE, I3,I2,I1, WE, rd2,ra2,re2,rh2,rl2,rc2,rk2,rn2,rb2,rp2,rg2,rm2,ro2,rf2,rj2,ri2, } Multiplexer assignment for block A A0 (MC17 P) : MUX 0 Ref (A13p) I3 (MC25 P) : MUX 1 Ref (F83p) A2 (MC19 P) : MUX 2 Ref (B27p) rd2 (MC1 FB) : MUX 4 Ref (A1fb) ra2 (MC4 FB) : MUX 5 Ref (A12fb) re2 (MC6 FB) : MUX 6 Ref (B18fb) A1 (MC18 P) : MUX 8 Ref (A14p) CE (MC21 P) : MUX 10 Ref (C43p) rh2 (MC11 FB) : MUX 11 Ref (D58fb) rl2 (MC9 FB) : MUX 12 Ref (D54fb) WE (MC22 P) : MUX 14 Ref (C45p) rc2 (MC3 FB) : MUX 15 Ref (A9fb) rk2 (MC12 FB) : MUX 17 Ref (D59fb) rn2 (MC14 FB) : MUX 18 Ref (E66fb) rb2 (MC2 FB) : MUX 20 Ref (A4fb) rp2 (MC15 FB) : MUX 24 Ref (E69fb) rg2 (MC5 FB) : MUX 26 Ref (B17fb) I2 (MC24 P) : MUX 28 Ref (D62p) rm2 (MC8 FB) : MUX 30 Ref (D49fb) ro2 (MC16 FB) : MUX 31 Ref (E75fb) A3 (MC20 P) : MUX 32 Ref (B29p) rf2 (MC7 FB) : MUX 34 Ref (B22fb) I1 (MC23 P) : MUX 36 Ref (D61p) rj2 (MC10 FB) : MUX 38 Ref (D55fb) ri2 (MC13 FB) : MUX 39 Ref (D60fb) FanIn assignment for block B [25] { A0,A2,A3,A1, CE, I4,I2,I1, WE, ro1,rc1,rd1,rf1,rj1,rg1,rl1,rk1,rp1,rn1,ra1,rm1,re1,rh1,ri1,rb1, } Multiplexer assignment for block B A0 (MC17 P) : MUX 0 Ref (A13p) ro1 (MC16 FB) : MUX 1 Ref (E77fb) A2 (MC19 P) : MUX 2 Ref (B27p) rc1 (MC3 FB) : MUX 4 Ref (A8fb) rd1 (MC2 FB) : MUX 6 Ref (A3fb) rf1 (MC7 FB) : MUX 7 Ref (B25fb) rj1 (MC8 FB) : MUX 8 Ref (C37fb) CE (MC21 P) : MUX 10 Ref (C43p) rg1 (MC5 FB) : MUX 12 Ref (B21fb) rl1 (MC13 FB) : MUX 13 Ref (D57fb) WE (MC22 P) : MUX 14 Ref (C45p) A3 (MC20 P) : MUX 16 Ref (B29p) rk1 (MC12 FB) : MUX 18 Ref (D52fb) rp1 (MC15 FB) : MUX 20 Ref (E70fb) A1 (MC18 P) : MUX 22 Ref (A14p) rn1 (MC14 FB) : MUX 24 Ref (E68fb) I4 (MC25 P) : MUX 25 Ref (F81p) ra1 (MC4 FB) : MUX 27 Ref (A10fb) I2 (MC24 P) : MUX 28 Ref (D62p) rm1 (MC11 FB) : MUX 30 Ref (D51fb) re1 (MC6 FB) : MUX 32 Ref (B23fb) rh1 (MC9 FB) : MUX 34 Ref (C39fb) ri1 (MC10 FB) : MUX 35 Ref (C41fb) I1 (MC23 P) : MUX 36 Ref (D61p) rb1 (MC1 FB) : MUX 38 Ref (A2fb) FanIn assignment for block C [25] { A0,A2,A1,A3, CE, I3,I4,I1, WE, rb3,rk3,rd3,rl3,ra3,rn3,rj3,rg3,rf3,ri3,rh3,re3,rc3,ro3,rp3,rm3, } Multiplexer assignment for block C A0 (MC17 P) : MUX 0 Ref (A13p) I3 (MC25 P) : MUX 1 Ref (F83p) A2 (MC19 P) : MUX 2 Ref (B27p) rb3 (MC4 FB) : MUX 3 Ref (A11fb) rk3 (MC15 FB) : MUX 5 Ref (E79fb) rd3 (MC1 FB) : MUX 6 Ref (A5fb) rl3 (MC14 FB) : MUX 7 Ref (E76fb) ra3 (MC3 FB) : MUX 8 Ref (A7fb) rn3 (MC16 FB) : MUX 9 Ref (E80fb) CE (MC21 P) : MUX 10 Ref (C43p) I4 (MC24 P) : MUX 11 Ref (F81p) A1 (MC18 P) : MUX 12 Ref (A14p) rj3 (MC5 FB) : MUX 14 Ref (C33fb) rg3 (MC8 FB) : MUX 15 Ref (C42fb) A3 (MC20 P) : MUX 16 Ref (B29p) WE (MC22 P) : MUX 18 Ref (C45p) rf3 (MC10 FB) : MUX 21 Ref (C48fb) ri3 (MC6 FB) : MUX 24 Ref (C38fb) rh3 (MC7 FB) : MUX 28 Ref (C40fb) re3 (MC9 FB) : MUX 29 Ref (C47fb) rc3 (MC2 FB) : MUX 34 Ref (A6fb) I1 (MC23 P) : MUX 36 Ref (D61p) ro3 (MC12 FB) : MUX 37 Ref (E73fb) rp3 (MC11 FB) : MUX 38 Ref (E67fb) rm3 (MC13 FB) : MUX 39 Ref (E74fb) FanIn assignment for block D [25] { A0,A2,A1,A3, CE, I4,I2,I1, WE, ra4,rd4,rp4,re4,rn4,rk4,rf4,rc4,ro4,rl4,rg4,rh4,rb4,ri4,rj4,rm4, } Multiplexer assignment for block D A0 (MC17 P) : MUX 0 Ref (A13p) A2 (MC19 P) : MUX 2 Ref (B27p) ra4 (MC5 FB) : MUX 3 Ref (B31fb) rd4 (MC2 FB) : MUX 4 Ref (B20fb) rp4 (MC13 FB) : MUX 6 Ref (E65fb) A1 (MC18 P) : MUX 8 Ref (A14p) CE (MC21 P) : MUX 10 Ref (C43p) I4 (MC25 P) : MUX 11 Ref (F81p) re4 (MC3 FB) : MUX 12 Ref (B24fb) I2 (MC24 P) : MUX 14 Ref (D62p) A3 (MC20 P) : MUX 16 Ref (B29p) rn4 (MC16 FB) : MUX 17 Ref (E78fb) rk4 (MC12 FB) : MUX 18 Ref (D56fb) rf4 (MC1 FB) : MUX 20 Ref (B19fb) rc4 (MC4 FB) : MUX 21 Ref (B26fb) ro4 (MC15 FB) : MUX 22 Ref (E72fb) rl4 (MC11 FB) : MUX 24 Ref (D53fb) rg4 (MC9 FB) : MUX 26 Ref (C36fb) rh4 (MC7 FB) : MUX 28 Ref (C34fb) rb4 (MC6 FB) : MUX 29 Ref (B32fb) ri4 (MC8 FB) : MUX 30 Ref (C35fb) rj4 (MC10 FB) : MUX 32 Ref (D50fb) WE (MC22 P) : MUX 34 Ref (C45p) I1 (MC23 P) : MUX 36 Ref (D61p) rm4 (MC14 FB) : MUX 38 Ref (E71fb) FanIn assignment for block E [10] { A0,A1,A3,A2, CE, I3,I4,I1,I2, WE, } Multiplexer assignment for block E CE (MC5 P) : MUX 0 Ref (C43p) I3 (MC10 P) : MUX 1 Ref (F83p) I4 (MC9 P) : MUX 3 Ref (F81p) A0 (MC1 P) : MUX 6 Ref (A13p) I1 (MC7 P) : MUX 8 Ref (D61p) A1 (MC2 P) : MUX 12 Ref (A14p) WE (MC6 P) : MUX 14 Ref (C45p) A3 (MC4 P) : MUX 16 Ref (B29p) A2 (MC3 P) : MUX 20 Ref (B27p) I2 (MC8 P) : MUX 28 Ref (D62p) Creating JEDEC file C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M8416\TOPLD\SN74189.jed ... TQFP100 programmed logic: ----------------------------------- !d3 = ((!A0 & !A1 & !A2 & !A3 & ra3.Q) # (A0 & !A1 & !A2 & !A3 & rb3.Q) # (!A0 & A1 & !A2 & !A3 & rc3.Q) # (A0 & A1 & !A2 & !A3 & rd3.Q) # (!A0 & !A1 & A2 & !A3 & re3.Q) # (A0 & !A1 & A2 & !A3 & rf3.Q) # (!A0 & A1 & A2 & !A3 & rg3.Q) # (A0 & A1 & A2 & !A3 & rh3.Q) # (!A0 & !A1 & !A2 & A3 & ri3.Q) # (A0 & !A1 & !A2 & A3 & rj3.Q) # (!A0 & A1 & !A2 & A3 & rk3.Q) # (A0 & A1 & !A2 & A3 & rl3.Q) # (!A0 & !A1 & A2 & A3 & rm3.Q) # (A0 & !A1 & A2 & A3 & rn3.Q) # (!A0 & A1 & A2 & A3 & ro3.Q) # (A0 & A1 & A2 & A3 & rp3.Q)); !d1 = ((!A0 & !A1 & !A2 & !A3 & ra1.Q) # (A0 & !A1 & !A2 & !A3 & rb1.Q) # (!A0 & A1 & !A2 & !A3 & rc1.Q) # (A0 & A1 & !A2 & !A3 & rd1.Q) # (!A0 & !A1 & A2 & !A3 & re1.Q) # (A0 & !A1 & A2 & !A3 & rf1.Q) # (!A0 & A1 & A2 & !A3 & rg1.Q) # (A0 & A1 & A2 & !A3 & rh1.Q) # (!A0 & !A1 & !A2 & A3 & ri1.Q) # (A0 & !A1 & !A2 & A3 & rj1.Q) # (!A0 & A1 & !A2 & A3 & rk1.Q) # (A0 & A1 & !A2 & A3 & rl1.Q) # (!A0 & !A1 & A2 & A3 & rm1.Q) # (A0 & !A1 & A2 & A3 & rn1.Q) # (!A0 & A1 & A2 & A3 & ro1.Q) # (A0 & A1 & A2 & A3 & rp1.Q)); !d2 = ((!A0 & !A1 & !A2 & !A3 & ra2.Q) # (A0 & !A1 & !A2 & !A3 & rb2.Q) # (!A0 & A1 & !A2 & !A3 & rc2.Q) # (A0 & A1 & !A2 & !A3 & rd2.Q) # (!A0 & !A1 & A2 & !A3 & re2.Q) # (A0 & !A1 & A2 & !A3 & rf2.Q) # (!A0 & A1 & A2 & !A3 & rg2.Q) # (A0 & A1 & A2 & !A3 & rh2.Q) # (!A0 & !A1 & !A2 & A3 & ri2.Q) # (A0 & !A1 & !A2 & A3 & rj2.Q) # (!A0 & A1 & !A2 & A3 & rk2.Q) # (A0 & A1 & !A2 & A3 & rl2.Q) # (!A0 & !A1 & A2 & A3 & rm2.Q) # (A0 & !A1 & A2 & A3 & rn2.Q) # (!A0 & A1 & A2 & A3 & ro2.Q) # (A0 & A1 & A2 & A3 & rp2.Q)); !d4 = ((!A0 & !A1 & !A2 & !A3 & ra4.Q) # (A0 & !A1 & !A2 & !A3 & rb4.Q) # (!A0 & A1 & !A2 & !A3 & rc4.Q) # (A0 & A1 & !A2 & !A3 & rd4.Q) # (!A0 & !A1 & A2 & !A3 & re4.Q) # (A0 & !A1 & A2 & !A3 & rf4.Q) # (!A0 & A1 & A2 & !A3 & rg4.Q) # (A0 & A1 & A2 & !A3 & rh4.Q) # (!A0 & !A1 & !A2 & A3 & ri4.Q) # (A0 & !A1 & !A2 & A3 & rj4.Q) # (!A0 & A1 & !A2 & A3 & rk4.Q) # (A0 & A1 & !A2 & A3 & rl4.Q) # (!A0 & !A1 & A2 & A3 & rm4.Q) # (A0 & !A1 & A2 & A3 & rn4.Q) # (!A0 & A1 & A2 & A3 & ro4.Q) # (A0 & A1 & A2 & A3 & rp4.Q)); ra2.L = I2; ra1.L = I1; ra3.L = I3; rb1.L = I1; ra4.L = I4; rb2.L = I2; rb4.L = I4; rb3.L = I3; rc1.L = I1; rc3.L = I3; rc2.L = I2; rc4.L = I4; rd2.L = I2; rd1.L = I1; rd4.L = I4; rd3.L = I3; re1.L = I1; re2.L = I2; re4.L = I4; re3.L = I3; rf1.L = I1; rf3.L = I3; rf2.L = I2; rf4.L = I4; rg1.L = I1; rg2.L = I2; rg4.L = I4; rg3.L = I3; rh1.L = I1; rh3.L = I3; rh2.L = I2; ri2.L = I2; rh4.L = I4; ri1.L = I1; ri3.L = I3; rj1.L = I1; ri4.L = I4; rj2.L = I2; rj4.L = I4; rj3.L = I3; rk1.L = I1; rk3.L = I3; rk2.L = I2; rk4.L = I4; rl2.L = I2; rl1.L = I1; rl3.L = I3; rl4.L = I4; rm1.L = I1; rm3.L = I3; rm2.L = I2; rm4.L = I4; rn2.L = I2; rn1.L = I1; rn3.L = I3; ro1.L = I1; rn4.L = I4; ro2.L = I2; ro4.L = I4; ro3.L = I3; rp1.L = I1; rp3.L = I3; rp2.L = I2; rp4.L = I4; ra2.LE = (!A0 & !A1 & !A2 & !A3 & !CE & !WE); ra1.LE = (!A0 & !A1 & !A2 & !A3 & !CE & !WE); ra3.LE = (!A0 & !A1 & !A2 & !A3 & !CE & !WE); rb1.LE = (A0 & !A1 & !A2 & !A3 & !CE & !WE); ra4.LE = (!A0 & !A1 & !A2 & !A3 & !CE & !WE); rb2.LE = (A0 & !A1 & !A2 & !A3 & !CE & !WE); rb4.LE = (A0 & !A1 & !A2 & !A3 & !CE & !WE); rb3.LE = (A0 & !A1 & !A2 & !A3 & !CE & !WE); rc1.LE = (!A0 & A1 & !A2 & !A3 & !CE & !WE); rc3.LE = (!A0 & A1 & !A2 & !A3 & !CE & !WE); rc2.LE = (!A0 & A1 & !A2 & !A3 & !CE & !WE); rc4.LE = (!A0 & A1 & !A2 & !A3 & !CE & !WE); rd2.LE = (A0 & A1 & !A2 & !A3 & !CE & !WE); rd1.LE = (A0 & A1 & !A2 & !A3 & !CE & !WE); rd4.LE = (A0 & A1 & !A2 & !A3 & !CE & !WE); rd3.LE = (A0 & A1 & !A2 & !A3 & !CE & !WE); re1.LE = (!A0 & !A1 & A2 & !A3 & !CE & !WE); re2.LE = (!A0 & !A1 & A2 & !A3 & !CE & !WE); re4.LE = (!A0 & !A1 & A2 & !A3 & !CE & !WE); re3.LE = (!A0 & !A1 & A2 & !A3 & !CE & !WE); rf1.LE = (A0 & !A1 & A2 & !A3 & !CE & !WE); rf3.LE = (A0 & !A1 & A2 & !A3 & !CE & !WE); rf2.LE = (A0 & !A1 & A2 & !A3 & !CE & !WE); rf4.LE = (A0 & !A1 & A2 & !A3 & !CE & !WE); rg1.LE = (!A0 & A1 & A2 & !A3 & !CE & !WE); rg2.LE = (!A0 & A1 & A2 & !A3 & !CE & !WE); rg4.LE = (!A0 & A1 & A2 & !A3 & !CE & !WE); rg3.LE = (!A0 & A1 & A2 & !A3 & !CE & !WE); rh1.LE = (A0 & A1 & A2 & !A3 & !CE & !WE); rh3.LE = (A0 & A1 & A2 & !A3 & !CE & !WE); rh2.LE = (A0 & A1 & A2 & !A3 & !CE & !WE); ri2.LE = (!A0 & !A1 & !A2 & A3 & !CE & !WE); rh4.LE = (A0 & A1 & A2 & !A3 & !CE & !WE); ri1.LE = (!A0 & !A1 & !A2 & A3 & !CE & !WE); ri3.LE = (!A0 & !A1 & !A2 & A3 & !CE & !WE); rj1.LE = (A0 & !A1 & !A2 & A3 & !CE & !WE); ri4.LE = (!A0 & !A1 & !A2 & A3 & !CE & !WE); rj2.LE = (A0 & !A1 & !A2 & A3 & !CE & !WE); rj4.LE = (A0 & !A1 & !A2 & A3 & !CE & !WE); rj3.LE = (A0 & !A1 & !A2 & A3 & !CE & !WE); rk1.LE = (!A0 & A1 & !A2 & A3 & !CE & !WE); rk3.LE = (!A0 & A1 & !A2 & A3 & !CE & !WE); rk2.LE = (!A0 & A1 & !A2 & A3 & !CE & !WE); rk4.LE = (!A0 & A1 & !A2 & A3 & !CE & !WE); rl2.LE = (A0 & A1 & !A2 & A3 & !CE & !WE); rl1.LE = (A0 & A1 & !A2 & A3 & !CE & !WE); rl3.LE = (A0 & A1 & !A2 & A3 & !CE & !WE); rl4.LE = (A0 & A1 & !A2 & A3 & !CE & !WE); rm1.LE = (!A0 & !A1 & A2 & A3 & !CE & !WE); rm3.LE = (!A0 & !A1 & A2 & A3 & !CE & !WE); rm2.LE = (!A0 & !A1 & A2 & A3 & !CE & !WE); rm4.LE = (!A0 & !A1 & A2 & A3 & !CE & !WE); rn2.LE = (A0 & !A1 & A2 & A3 & !CE & !WE); rn1.LE = (A0 & !A1 & A2 & A3 & !CE & !WE); rn3.LE = (A0 & !A1 & A2 & A3 & !CE & !WE); ro1.LE = (!A0 & A1 & A2 & A3 & !CE & !WE); rn4.LE = (A0 & !A1 & A2 & A3 & !CE & !WE); ro2.LE = (!A0 & A1 & A2 & A3 & !CE & !WE); ro4.LE = (!A0 & A1 & A2 & A3 & !CE & !WE); ro3.LE = (!A0 & A1 & A2 & A3 & !CE & !WE); rp1.LE = (A0 & A1 & A2 & A3 & !CE & !WE); rp3.LE = (A0 & A1 & A2 & A3 & !CE & !WE); rp2.LE = (A0 & A1 & A2 & A3 & !CE & !WE); rp4.LE = (A0 & A1 & A2 & A3 & !CE & !WE); TQFP100 Pin/Node Placement: ------------------------------------ Pin 4 = TDI; /* MC 32 */ Pin 5 = d1; /* MC 30 */ Pin 6 = A3; /* MC 29 */ Pin 7 = A2; /* MC 27 */ Pin 15 = TMS; /* MC 48 */ Pin 16 = d3; /* MC 46 */ Pin 17 = WE; /* MC 45 */ Pin 19 = CE; /* MC 43 */ Pin 27 = d4; /* MC 64 */ Pin 28 = I2; /* MC 62 */ Pin 29 = I1; /* MC 61 */ Pin 52 = I4; /* MC 81 */ Pin 53 = I3; /* MC 83 */ Pin 62 = TCK; /* MC 96 */ Pin 73 = TDO; /* MC 112 */ Pin 92 = d2; /* MC 16 */ Pin 93 = A1; /* MC 14 */ Pin 94 = A0; /* MC 13 */ PINNODE 601 = rd2; /* MC 1 Feedback */ PINNODE 602 = rb1; /* MC 2 Feedback */ PINNODE 603 = rd1; /* MC 3 Feedback */ PINNODE 604 = rb2; /* MC 4 Feedback */ PINNODE 605 = rd3; /* MC 5 Feedback */ PINNODE 606 = rc3; /* MC 6 Feedback */ PINNODE 607 = ra3; /* MC 7 Feedback */ PINNODE 608 = rc1; /* MC 8 Feedback */ PINNODE 609 = rc2; /* MC 9 Feedback */ PINNODE 610 = ra1; /* MC 10 Feedback */ PINNODE 611 = rb3; /* MC 11 Feedback */ PINNODE 612 = ra2; /* MC 12 Feedback */ PINNODE 617 = rg2; /* MC 17 Feedback */ PINNODE 618 = re2; /* MC 18 Feedback */ PINNODE 619 = rf4; /* MC 19 Feedback */ PINNODE 620 = rd4; /* MC 20 Feedback */ PINNODE 621 = rg1; /* MC 21 Feedback */ PINNODE 622 = rf2; /* MC 22 Feedback */ PINNODE 623 = re1; /* MC 23 Feedback */ PINNODE 624 = re4; /* MC 24 Feedback */ PINNODE 625 = rf1; /* MC 25 Feedback */ PINNODE 626 = rc4; /* MC 26 Feedback */ PINNODE 631 = ra4; /* MC 31 Feedback */ PINNODE 632 = rb4; /* MC 32 Feedback */ PINNODE 633 = rj3; /* MC 33 Feedback */ PINNODE 634 = rh4; /* MC 34 Feedback */ PINNODE 635 = ri4; /* MC 35 Feedback */ PINNODE 636 = rg4; /* MC 36 Feedback */ PINNODE 637 = rj1; /* MC 37 Feedback */ PINNODE 638 = ri3; /* MC 38 Feedback */ PINNODE 639 = rh1; /* MC 39 Feedback */ PINNODE 640 = rh3; /* MC 40 Feedback */ PINNODE 641 = ri1; /* MC 41 Feedback */ PINNODE 642 = rg3; /* MC 42 Feedback */ PINNODE 647 = re3; /* MC 47 Feedback */ PINNODE 648 = rf3; /* MC 48 Feedback */ PINNODE 649 = rm2; /* MC 49 Feedback */ PINNODE 650 = rj4; /* MC 50 Feedback */ PINNODE 651 = rm1; /* MC 51 Feedback */ PINNODE 652 = rk1; /* MC 52 Feedback */ PINNODE 653 = rl4; /* MC 53 Feedback */ PINNODE 654 = rl2; /* MC 54 Feedback */ PINNODE 655 = rj2; /* MC 55 Feedback */ PINNODE 656 = rk4; /* MC 56 Feedback */ PINNODE 657 = rl1; /* MC 57 Feedback */ PINNODE 658 = rh2; /* MC 58 Feedback */ PINNODE 659 = rk2; /* MC 59 Feedback */ PINNODE 660 = ri2; /* MC 60 Feedback */ PINNODE 665 = rp4; /* MC 65 Feedback */ PINNODE 666 = rn2; /* MC 66 Feedback */ PINNODE 667 = rp3; /* MC 67 Feedback */ PINNODE 668 = rn1; /* MC 68 Feedback */ PINNODE 669 = rp2; /* MC 69 Feedback */ PINNODE 670 = rp1; /* MC 70 Feedback */ PINNODE 671 = rm4; /* MC 71 Feedback */ PINNODE 672 = ro4; /* MC 72 Feedback */ PINNODE 673 = ro3; /* MC 73 Feedback */ PINNODE 674 = rm3; /* MC 74 Feedback */ PINNODE 675 = ro2; /* MC 75 Feedback */ PINNODE 676 = rl3; /* MC 76 Feedback */ PINNODE 677 = ro1; /* MC 77 Feedback */ PINNODE 678 = rn4; /* MC 78 Feedback */ PINNODE 679 = rk3; /* MC 79 Feedback */ PINNODE 680 = rn3; /* MC 80 Feedback */ ** Resource Usage ** DCERP Field = Summary of Allocations. ||||| |||||_Preset [p,-] == p = PT preset, - No Preset. |||| ||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset. ||| |||___Clock Enable [e,-] == e = Product Term, - always enabled, - none. || ||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock. | |_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff. For input only = INPUT. MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT output_slew MC1 2 -- rd2 Lc--- -- -- 2 slow MC2 0 -- rb1 Lc--- -- -- 2 slow MC3 1 -- rd1 Lc--- -- -- 2 slow MC4 0 -- rb2 Lc--- -- -- 2 slow MC5 100 -- rd3 Lc--- -- -- 2 slow MC6 99 -- rc3 Lc--- -- -- 2 slow MC7 0 -- ra3 Lc--- -- -- 2 slow MC8 98 -- rc1 Lc--- -- -- 2 slow MC9 97 -- rc2 Lc--- -- -- 2 slow MC10 0 -- ra1 Lc--- -- -- 2 slow MC11 96 -- rb3 Lc--- -- -- 2 slow MC12 0 -- ra2 Lc--- -- -- 2 slow MC13 94 -- A0 INPUT -- -- -> d2 5 slow MC14 93 -- A1 INPUT -- -- -> d2 5 slow MC15 0 -- -- -- -> d2 5 slow MC16 92 on d2 C---- -- -- -- 1 slow MC17 14 -- rg2 Lc--- -- -- 2 slow MC18 0 -- re2 Lc--- -- -- 2 slow MC19 13 -- rf4 Lc--- -- -- 2 slow MC20 0 -- rd4 Lc--- -- -- 2 slow MC21 12 -- rg1 Lc--- -- -- 2 slow MC22 10 -- rf2 Lc--- -- -- 2 slow MC23 0 -- re1 Lc--- -- -- 2 slow MC24 9 -- re4 Lc--- -- -- 2 slow MC25 8 -- rf1 Lc--- -- -- 2 slow MC26 0 -- rc4 Lc--- -- -- 2 slow MC27 7 -- A2 INPUT -- -- -> d1 5 slow MC28 0 -- -- -- -> d1 5 slow MC29 6 -- A3 INPUT -- -- -> d1 5 slow MC30 5 on d1 C---- -- -- -- 1 slow MC31 0 -- ra4 Lc--- -- -- 2 slow MC32 4 -- TDI INPUT rb4 Lc--- -- -- 2 slow MC33 25 -- rj3 Lc--- -- -- 2 slow MC34 0 -- rh4 Lc--- -- -- 2 slow MC35 24 -- ri4 Lc--- -- -- 2 slow MC36 0 -- rg4 Lc--- -- -- 2 slow MC37 23 -- rj1 Lc--- -- -- 2 slow MC38 22 -- ri3 Lc--- -- -- 2 slow MC39 0 -- rh1 Lc--- -- -- 2 slow MC40 21 -- rh3 Lc--- -- -- 2 slow MC41 20 -- ri1 Lc--- -- -- 2 slow MC42 0 -- rg3 Lc--- -- -- 2 slow MC43 19 -- CE INPUT -- -- -> d3 5 slow MC44 0 -- -- -- -> d3 5 slow MC45 17 -- WE INPUT -- -- -> d3 5 slow MC46 16 on d3 C---- -- -- -- 1 slow MC47 0 -- re3 Lc--- -- -- 2 slow MC48 15 -- TMS INPUT rf3 Lc--- -- -- 2 slow MC49 37 -- rm2 Lc--- -- -- 2 slow MC50 0 -- rj4 Lc--- -- -- 2 slow MC51 36 -- rm1 Lc--- -- -- 2 slow MC52 0 -- rk1 Lc--- -- -- 2 slow MC53 35 -- rl4 Lc--- -- -- 2 slow MC54 33 -- rl2 Lc--- -- -- 2 slow MC55 0 -- rj2 Lc--- -- -- 2 slow MC56 32 -- rk4 Lc--- -- -- 2 slow MC57 31 -- rl1 Lc--- -- -- 2 slow MC58 0 -- rh2 Lc--- -- -- 2 slow MC59 30 -- rk2 Lc--- -- -- 2 slow MC60 0 -- ri2 Lc--- -- -- 2 slow MC61 29 -- I1 INPUT -- -- -> d4 5 slow MC62 28 -- I2 INPUT -- -- -> d4 5 slow MC63 0 -- -- -- -> d4 5 slow MC64 27 on d4 C---- -- -- -- 1 slow MC65 40 -- rp4 Lc--- -- -- 2 slow MC66 0 -- rn2 Lc--- -- -- 2 slow MC67 41 -- rp3 Lc--- -- -- 2 slow MC68 0 -- rn1 Lc--- -- -- 2 slow MC69 42 -- rp2 Lc--- -- -- 2 slow MC70 44 -- rp1 Lc--- -- -- 2 slow MC71 0 -- rm4 Lc--- -- -- 2 slow MC72 45 -- ro4 Lc--- -- -- 2 slow MC73 46 -- ro3 Lc--- -- -- 2 slow MC74 0 -- rm3 Lc--- -- -- 2 slow MC75 47 -- ro2 Lc--- -- -- 2 slow MC76 0 -- rl3 Lc--- -- -- 2 slow MC77 48 -- ro1 Lc--- -- -- 2 slow MC78 49 -- rn4 Lc--- -- -- 2 slow MC79 0 -- rk3 Lc--- -- -- 2 slow MC80 50 -- rn3 Lc--- -- -- 2 slow MC81 52 -- I4 INPUT -- -- -- 0 slow MC82 0 -- -- -- -- 0 slow MC83 53 -- I3 INPUT -- -- -- 0 slow MC84 0 -- -- -- -- 0 slow MC85 54 -- -- -- -- 0 slow MC86 55 -- -- -- -- 0 slow MC87 0 -- -- -- -- 0 slow MC88 56 -- -- -- -- 0 slow MC89 57 -- -- -- -- 0 slow MC90 0 -- -- -- -- 0 slow MC91 58 -- -- -- -- 0 slow MC92 0 -- -- -- -- 0 slow MC93 60 -- -- -- -- 0 slow MC94 61 -- -- -- -- 0 slow MC95 0 -- -- -- -- 0 slow MC96 62 -- TCK INPUT -- -- -- 0 slow MC97 63 -- -- -- -- 0 slow MC98 0 -- -- -- -- 0 slow MC99 64 -- -- -- -- 0 slow MC100 0 -- -- -- -- 0 slow MC101 65 -- -- -- -- 0 slow MC102 67 -- -- -- -- 0 slow MC103 0 -- -- -- -- 0 slow MC104 68 -- -- -- -- 0 slow MC105 69 -- -- -- -- 0 slow MC106 0 -- -- -- -- 0 slow MC107 70 -- -- -- -- 0 slow MC108 0 -- -- -- -- 0 slow MC109 71 -- -- -- -- 0 slow MC110 72 -- -- -- -- 0 slow MC111 0 -- -- -- -- 0 slow MC112 73 -- TDO INPUT -- -- -- 0 slow MC113 75 -- -- -- -- 0 slow MC114 0 -- -- -- -- 0 slow MC115 76 -- -- -- -- 0 slow MC116 0 -- -- -- -- 0 slow MC117 77 -- -- -- -- 0 slow MC118 78 -- -- -- -- 0 slow MC119 0 -- -- -- -- 0 slow MC120 79 -- -- -- -- 0 slow MC121 80 -- -- -- -- 0 slow MC122 0 -- -- -- -- 0 slow MC123 81 -- -- -- -- 0 slow MC124 0 -- -- -- -- 0 slow MC125 83 -- -- -- -- 0 slow MC126 84 -- -- -- -- 0 slow MC127 0 -- -- -- -- 0 slow MC128 85 -- -- -- -- 0 slow MC0 90 -- -- -- -- 0 slow MC0 89 -- -- -- -- 0 slow MC0 88 -- -- -- -- 0 slow MC0 87 -- -- -- -- 0 slow Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades A: LC1 - LC16 13/16(81%) 3/16(18%) 0/16(0%) 40/80(50%) (25) 3 B: LC17 - LC32 13/16(81%) 4/16(25%) 0/16(0%) 40/80(50%) (25) 3 C: LC33 - LC48 13/16(81%) 4/16(25%) 0/16(0%) 40/80(50%) (25) 3 D: LC49 - LC64 13/16(81%) 3/16(18%) 0/16(0%) 40/80(50%) (25) 3 E: LC65 - LC80 16/16(100%) 0/16(0%) 0/16(0%) 32/80(40%) (10) 0 F: LC81 - LC96 0/16(0%) 3/16(18%) 0/16(0%) 0/80(0%) (0) 0 G: LC97 - LC112 0/16(0%) 1/16(6%) 0/16(0%) 0/80(0%) (0) 0 H: LC113- LC128 0/16(0%) 0/16(0%) 0/16(0%) 0/80(0%) (0) 0 Total dedicated input used: 0/4 (0%) Total I/O pins used 18/80 (22%) Total Logic cells used 80/128 (62%) Total Flip-Flop used 64/128 (50%) Total Foldback logic used 0/128 (0%) Total Nodes+FB/MCells 68/128 (53%) Total cascade used 12 Total input pins 14 Total output pins 4 Total Pts 192 Creating pla file C:\USERS\VINCE\DOCUMENTS\EAGLE\PROJECTS\DEC\MXXX\M8416\TOPLD\SN74189.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms... ---------------- End fitter, Design FITS $Device TQFP100 fits FIT1508 completed in 0.00 seconds