# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 18:11:05 October 18, 2021 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # M8650_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY MAX7000S set_global_assignment -name DEVICE "EPM7128SLC84-15" set_global_assignment -name TOP_LEVEL_ENTITY m8650 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:11:05 OCTOBER 18, 2021" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84 set_global_assignment -name SLOW_SLEW_RATE ON set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL set_location_assignment PIN_39 -to power_ok set_location_assignment PIN_35 -to c0_l set_location_assignment PIN_33 -to c1_l set_location_assignment PIN_31 -to tp3 set_location_assignment PIN_1 -to sw1 set_location_assignment PIN_84 -to sw2 set_location_assignment PIN_74 -to sw3 set_location_assignment PIN_75 -to serial_in set_location_assignment PIN_76 -to serial_out set_location_assignment PIN_22 -to skip_l set_location_assignment PIN_6 -to md11_l set_location_assignment PIN_61 -to md03_l set_location_assignment PIN_52 -to md04_l set_location_assignment PIN_51 -to md05_l set_location_assignment PIN_50 -to md06_l set_location_assignment PIN_49 -to md07_l set_location_assignment PIN_12 -to md08_l set_location_assignment PIN_10 -to md09_l set_location_assignment PIN_9 -to md10_l set_location_assignment PIN_36 -to io_pause_l set_location_assignment PIN_46 -to data04_l set_location_assignment PIN_45 -to data05_l set_location_assignment PIN_44 -to data06_l set_location_assignment PIN_40 -to data07_l set_location_assignment PIN_4 -to data08_l set_location_assignment PIN_81 -to data09_l set_location_assignment PIN_80 -to data10_l set_location_assignment PIN_77 -to data11_l set_location_assignment PIN_24 -to initialize set_location_assignment PIN_25 -to int_rqst_l set_location_assignment PIN_28 -to internal_io_l set_location_assignment PIN_14 -to TDI set_location_assignment PIN_71 -to TDO set_location_assignment PIN_23 -to TMS set_location_assignment PIN_62 -to TCK set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" set_location_assignment PIN_37 -to tp_ca1 set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING NORMAL set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA set_location_assignment PIN_73 -to tp_ab1 set_location_assignment PIN_56 -to tp_ba1 set_location_assignment PIN_55 -to tp_bb1 set_location_assignment PIN_83 -to bd230400 set_global_assignment -name ENABLE_DA_RULE "A109, A110" set_global_assignment -name DISABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, S101, S102, S103, S104, D101, D102, D103" set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS OFF set_global_assignment -name VERILOG_FILE M8650.v