Atmel ATF1508AS Fitter Version 1.8.7.8 ,running Mon Oct 03 09:43:45 2016 fit1508 C:\USERS\MALCOLM\ONEDRIVE\OMNIBUS-SERIAL-BOARD\CUPL-FILES\MAIN.tt2 -CUPL -dev P1508C84 -JTAG ON ****** Initial fitting strategy and property ****** Pla_in_file = MAIN.tt2 Pla_out_file = MAIN.tt3 Jedec_file = MAIN.jed Vector_file = MAIN.tmv verilog_file = MAIN.vt Time_file = Log_file = MAIN.fit err_file = Device_name = PLCC84 Module_name = Package_type = PLCC Preassign_file = Property_file = Sleep_mode = Preassignment = Security_mode = OFF Pin_keep_mode = ON Dedicated_input_clock = Dedicated_input_reset = Dedicated_input_oe = supporter = CUPL optimize = ON Soft_buffer = Xor_synthesis = OFF Foldback_logic = on Expander = Cascade_logic = OFF Dedicated_input = Output_fast = OFF ******************************* Power down pin 1 = OFF Power down pin 2 = OFF power_reset = OFF JTAG = ON TDI pullup = ON TMS pullup = ON MC_power = OFF Open_collector = DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, DATA8, DATA9, DATA10, DATA11, INTERNAL_IO, C0, C1, SKIP, INT_RQST, ITD0 = ON ITD1 = ON ITD2 = ON Fast_inlatch = off ******************************* --------------------------------------------------------- Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF ... Info: C:\USERS\MALCOLM\ONEDRIVE\OMNIBUS-SERIAL-BOARD\CUPL-FILES\MAIN uses 90% of the logic resources in device PLCC84 If you wish to have more pins available for future logic change Atmel recommends using a larger device. Performing global Output Enable pin assignments ... Performing global pin assignments ... -------------------------------------- Final global control pins assignment (if applicable)... ------------------------------------------------------- CLK assigned to pin 81 Performing input pin pre-assignments ... ------------------------------------ RX_FLAG.AR equation needs patching. TX_FLAG.AR equation needs patching. 2 control equtions need patching Attempt to place floating signals ... ------------------------------------ TS9 is placed at feedback node 601 (MC 1) TS8 is placed at feedback node 602 (MC 2) RXA0 is placed at pin 12 (MC 3) TS7 is placed at feedback node 603 (MC 3) UART_TX is placed at pin 11 (MC 5) RXA1 is placed at pin 10 (MC 6) TS6 is placed at feedback node 606 (MC 6) TS5 is placed at feedback node 607 (MC 7) UART_RX is placed at pin 9 (MC 8) TS4 is placed at feedback node 608 (MC 8) TS3 is placed at feedback node 609 (MC 9) TS2 is placed at feedback node 610 (MC 10) TC1 is placed at feedback node 611 (MC 11) TS1 is placed at feedback node 612 (MC 12) TC2 is placed at feedback node 613 (MC 13) RC0 is placed at feedback node 614 (MC 14) XXL_580 is placed at foldback expander node 314 (MC 14) TS0 is placed at feedback node 615 (MC 15) XXL_568 is placed at foldback expander node 315 (MC 15) TS10 is placed at feedback node 616 (MC 16) Com_Ctrl_561 is placed at foldback expander node 316 (MC 16) DATA10 is placed at pin 22 (MC 17) TCK6 is placed at feedback node 618 (MC 18) DATA11 is placed at pin 21 (MC 19) TCK8 is placed at feedback node 620 (MC 20) TCK7 is placed at feedback node 621 (MC 21) TCK9 is placed at feedback node 622 (MC 22) TCK10 is placed at feedback node 623 (MC 23) RXA5 is placed at pin 18 (MC 24) TCK11 is placed at feedback node 624 (MC 24) RXA4 is placed at pin 17 (MC 25) TCK12 is placed at feedback node 625 (MC 25) Com_Ctrl_559 is placed at feedback node 626 (MC 26) RXA3 is placed at pin 16 (MC 27) TCK13 is placed at feedback node 627 (MC 27) RLC0 is placed at feedback node 628 (MC 28) RXA2 is placed at pin 15 (MC 29) RLC1 is placed at feedback node 629 (MC 29) RLC2 is placed at feedback node 630 (MC 30) RLC3 is placed at feedback node 631 (MC 31) TDI is placed at pin 14 (MC 32) RDRRUN is placed at feedback node 632 (MC 32) Com_Ctrl_560 is placed at foldback expander node 332 (MC 32) BC1 is placed at feedback node 633 (MC 33) BC0 is placed at feedback node 634 (MC 34) SKIP is placed at pin 31 (MC 35) BC2 is placed at feedback node 636 (MC 36) MD8 is placed at pin 30 (MC 37) BC4 is placed at feedback node 637 (MC 37) MD9 is placed at pin 29 (MC 38) BC3 is placed at feedback node 638 (MC 38) BC6 is placed at feedback node 639 (MC 39) MD10 is placed at pin 28 (MC 40) BC7 is placed at feedback node 640 (MC 40) BC5 is placed at feedback node 641 (MC 41) BC8 is placed at feedback node 642 (MC 42) MD11 is placed at pin 27 (MC 43) BC9 is placed at feedback node 643 (MC 43) BC10 is placed at feedback node 644 (MC 44) DATA9 is placed at pin 25 (MC 45) DATA8 is placed at pin 24 (MC 46) BC11 is placed at feedback node 647 (MC 47) TMS is placed at pin 23 (MC 48) RX_FLAG.AR is placed at feedback node 648 (MC 48) Com_Ctrl_562 is placed at foldback expander node 348 (MC 48) OMNI_IO_PAUSE is placed at pin 41 (MC 49) TSR4 is placed at feedback node 649 (MC 49) TSR2 is placed at feedback node 650 (MC 50) TP3 is placed at pin 40 (MC 51) TSR1 is placed at feedback node 651 (MC 51) TX_FLAG.AR is placed at feedback node 652 (MC 52) C0 is placed at pin 39 (MC 53) XXL_575 is placed at feedback node 654 (MC 54) XXL_609 is placed at foldback expander node 354 (MC 54) XXL_576 is placed at feedback node 655 (MC 55) C1 is placed at pin 37 (MC 56) INTERNAL_IO is placed at pin 36 (MC 57) XXL_624 is placed at feedback node 658 (MC 58) TSR3 is placed at feedback node 659 (MC 59) XXL_572 is placed at feedback node 660 (MC 60) INT_RQST is placed at pin 34 (MC 61) STROBE is placed at feedback node 662 (MC 62) TX_FLAG is placed at feedback node 663 (MC 63) INIT is placed at pin 33 (MC 64) TSR0 is placed at feedback node 664 (MC 64) TCK0 is placed at feedback node 665 (MC 65) TCK1 is placed at feedback node 666 (MC 66) DATA6 is placed at pin 45 (MC 67) TCK2 is placed at feedback node 668 (MC 68) DATA7 is placed at pin 46 (MC 69) TSR5 is placed at feedback node 670 (MC 70) TLC0 is placed at feedback node 671 (MC 71) Com_Ctrl_558 is placed at foldback expander node 371 (MC 71) DATA5 is placed at pin 48 (MC 72) MD7 is placed at pin 49 (MC 73) TSR6 is placed at feedback node 673 (MC 73) TCK4 is placed at feedback node 674 (MC 74) DATA4 is placed at pin 50 (MC 75) TSR7 is placed at feedback node 676 (MC 76) MD5 is placed at pin 51 (MC 77) TCK5 is placed at feedback node 677 (MC 77) CNTR_START is placed at feedback node 678 (MC 78) TLC1 is placed at feedback node 679 (MC 79) MD6 is placed at pin 52 (MC 80) TCK3 is placed at feedback node 680 (MC 80) RSR2 is placed at feedback node 681 (MC 81) RSR3 is placed at feedback node 682 (MC 82) DATA3 is placed at pin 54 (MC 83) RSR1 is placed at feedback node 684 (MC 84) MD4 is placed at pin 55 (MC 85) RSR0 is placed at feedback node 685 (MC 85) DATA1 is placed at pin 56 (MC 86) XXL_565 is placed at feedback node 687 (MC 87) DATA2 is placed at pin 57 (MC 88) XXL_570 is placed at feedback node 689 (MC 89) RSR7 is placed at feedback node 690 (MC 90) MD3 is placed at pin 58 (MC 91) TC0 is placed at feedback node 691 (MC 91) RX_FLAG is placed at feedback node 692 (MC 92) TLC3 is placed at feedback node 695 (MC 95) TCK is placed at pin 62 (MC 96) TLC2 is placed at feedback node 696 (MC 96) Com_Ctrl_558 is placed at foldback expander node 396 (MC 96) RSR5 is placed at feedback node 697 (MC 97) RS8 is placed at feedback node 698 (MC 98) RSR4 is placed at feedback node 699 (MC 99) RS6 is placed at feedback node 700 (MC 100) DATA0 is placed at pin 65 (MC 101) RS9 is placed at feedback node 702 (MC 102) XXL_579 is placed at foldback expander node 402 (MC 102) RS5 is placed at feedback node 703 (MC 103) RC1 is placed at feedback node 704 (MC 104) RC2 is placed at feedback node 705 (MC 105) RS4 is placed at feedback node 706 (MC 106) RS10 is placed at feedback node 707 (MC 107) RS3 is placed at feedback node 708 (MC 108) RS7 is placed at feedback node 709 (MC 109) RS1 is placed at feedback node 710 (MC 110) XXL_569 is placed at foldback expander node 410 (MC 110) RS2 is placed at feedback node 711 (MC 111) Com_Ctrl_561 is placed at foldback expander node 411 (MC 111) TDO is placed at pin 71 (MC 112) RS0 is placed at feedback node 712 (MC 112) LED1 is placed at pin 75 (MC 118) LED2 is placed at pin 77 (MC 123) LED0 is placed at pin 79 (MC 125) BR_CLR is placed at feedback node 727 (MC 127) CLK is placed at pin 81 (MC 128) RSR6 is placed at feedback node 728 (MC 128) U U A A R R T R T L L L _ X _ G V G C E V E E T A R N C N L D C D D X 1 X D C D K 0 C 2 1 ------------------------------------------- / 11 9 7 5 3 1 83 81 79 77 75 \ / 10 8 6 4 2 84 82 80 78 76 \ RXA0 | 12 (*) 74 | VCC | 13 73 | TDI | 14 72 | GND RXA2 | 15 71 | TDO RXA3 | 16 70 | RXA4 | 17 69 | RXA5 | 18 68 | GND | 19 67 | | 20 66 | VCC DATA11 | 21 65 | DATA0 DATA10 | 22 ATF1508 64 | TMS | 23 84-Lead PLCC 63 | DATA8 | 24 62 | TCK DATA9 | 25 61 | VCC | 26 60 | MD11 | 27 59 | GND MD10 | 28 58 | MD3 MD9 | 29 57 | DATA2 MD8 | 30 56 | DATA1 SKIP | 31 55 | MD4 GND | 32 54 | DATA3 \ 34 36 38 40 42 44 46 48 50 52 / \ 33 35 37 39 41 43 45 47 49 51 53/ -------------------------------------------- I I I C V C T O G V D D G D M D M M V N N N 1 C 0 P M N C A A N A D A D D C I T T C 3 N D C T T D T 7 T 5 6 C T _ E I A A A A R R _ 6 7 5 4 Q N I S A O T L _ _ P I A O U S E VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V) GND = GND pin which must be connected to ground TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface NC = Unused I/O pins which must be unconnected on the board Universal-Interconnect-Multiplexer assignments ------------------------------------------------ FanIn assignment for block A [26] { CNTR_START, RS0, STROBE, TS7,TS10,TSR5,TC1,TS4,TS1,TS0,TS5,TSR0,TSR2,TS3,TSR4,TC0,TSR3,TSR6,TSR7,TS9,TS8,TS2,TS6,TC2,TSR1, XXL_624, } Multiplexer assignment for block A TS7 (MC3 FB) : MUX 0 Ref (A3fb) TS10 (MC13 FB) : MUX 1 Ref (A16fb) TSR5 (MC21 FB) : MUX 2 Ref (E70fb) TC1 (MC9 FB) : MUX 3 Ref (A11fb) TS4 (MC6 FB) : MUX 4 Ref (A8fb) TS1 (MC10 FB) : MUX 5 Ref (A12fb) TS0 (MC12 FB) : MUX 7 Ref (A15fb) TS5 (MC5 FB) : MUX 8 Ref (A7fb) TSR0 (MC20 FB) : MUX 9 Ref (D64fb) TSR2 (MC15 FB) : MUX 10 Ref (D50fb) TS3 (MC7 FB) : MUX 11 Ref (A9fb) TSR4 (MC14 FB) : MUX 12 Ref (D49fb) TC0 (MC25 FB) : MUX 13 Ref (F91fb) CNTR_START (MC24 FB) : MUX 15 Ref (E78fb) TSR3 (MC18 FB) : MUX 17 Ref (D59fb) XXL_624 (MC17 FB) : MUX 19 Ref (D58fb) TSR6 (MC22 FB) : MUX 23 Ref (E73fb) TSR7 (MC23 FB) : MUX 25 Ref (E76fb) TS9 (MC1 FB) : MUX 26 Ref (A1fb) RS0 (MC26 FB) : MUX 27 Ref (G112fb) TS8 (MC2 FB) : MUX 28 Ref (A2fb) TS2 (MC8 FB) : MUX 29 Ref (A10fb) TS6 (MC4 FB) : MUX 32 Ref (A6fb) TC2 (MC11 FB) : MUX 33 Ref (A13fb) TSR1 (MC16 FB) : MUX 34 Ref (D51fb) STROBE (MC19 FB) : MUX 39 Ref (D62fb) FanIn assignment for block B [29] { Com_Ctrl_559, INIT, MD11,MD10,MD9, OMNI_IO_PAUSE, RS2,RSR1,RLC2,RSR0,RS10,RLC0,RLC1, TCK2,TCK11,TCK6,TCK0,TP3,TCK7,TCK10,TCK4,TCK12,TCK8,TCK3,TCK5,TCK9,TCK13,TCK1, XXL_575, } Multiplexer assignment for block B MD11 (MC26 P) : MUX 0 Ref (C43p) RS2 (MC23 FB) : MUX 1 Ref (G111fb) TCK2 (MC16 FB) : MUX 2 Ref (E68fb) MD10 (MC25 P) : MUX 3 Ref (C40p) TCK11 (MC6 FB) : MUX 4 Ref (B24fb) OMNI_IO_PAUSE (MC27 P) : MUX 5 Ref (D49p) TCK6 (MC1 FB) : MUX 6 Ref (B18fb) MD9 (MC24 P) : MUX 7 Ref (C38p) TCK0 (MC14 FB) : MUX 8 Ref (E65fb) TP3 (MC28 P) : MUX 9 Ref (D51p) TCK7 (MC3 FB) : MUX 10 Ref (B21fb) Com_Ctrl_559 (MC8 FB) : MUX 11 Ref (B26fb) INIT (MC29 P) : MUX 12 Ref (D64p) TCK10 (MC5 FB) : MUX 14 Ref (B23fb) TCK4 (MC17 FB) : MUX 15 Ref (E74fb) RSR1 (MC20 FB) : MUX 16 Ref (F84fb) TCK12 (MC7 FB) : MUX 17 Ref (B25fb) TCK8 (MC2 FB) : MUX 18 Ref (B20fb) RLC2 (MC12 FB) : MUX 19 Ref (B30fb) TCK3 (MC19 FB) : MUX 23 Ref (E80fb) TCK5 (MC18 FB) : MUX 25 Ref (E77fb) TCK9 (MC4 FB) : MUX 26 Ref (B22fb) RSR0 (MC21 FB) : MUX 28 Ref (F85fb) XXL_575 (MC13 FB) : MUX 30 Ref (D54fb) TCK13 (MC9 FB) : MUX 33 Ref (B27fb) TCK1 (MC15 FB) : MUX 34 Ref (E66fb) RS10 (MC22 FB) : MUX 35 Ref (G107fb) RLC0 (MC10 FB) : MUX 37 Ref (B28fb) RLC1 (MC11 FB) : MUX 39 Ref (B29fb) FanIn assignment for block C [26] { BC5,BC7,BC10,BC0,BR_CLR,BC9,BC6,BC8,BC2,BC4,BC1,BC3, INIT, LED0, MD11,MD10,MD9, OMNI_IO_PAUSE, RSR2,RX_FLAG,RSR3,RS10, TP3,TX_FLAG, XXL_575,XXL_576, } Multiplexer assignment for block C MD11 (MC23 P) : MUX 0 Ref (C43p) BC5 (MC8 FB) : MUX 1 Ref (C41fb) XXL_575 (MC12 FB) : MUX 2 Ref (D54fb) LED0 (MC19 P) : MUX 4 Ref (H125p) OMNI_IO_PAUSE (MC24 P) : MUX 5 Ref (D49p) BC7 (MC7 FB) : MUX 6 Ref (C40fb) BC10 (MC11 FB) : MUX 7 Ref (C44fb) RSR2 (MC15 FB) : MUX 8 Ref (F81fb) TP3 (MC25 P) : MUX 9 Ref (D51p) BC0 (MC2 FB) : MUX 10 Ref (C34fb) BR_CLR (MC20 FB) : MUX 11 Ref (H127fb) BC9 (MC10 FB) : MUX 13 Ref (C43fb) BC6 (MC6 FB) : MUX 14 Ref (C39fb) BC8 (MC9 FB) : MUX 15 Ref (C42fb) XXL_576 (MC13 FB) : MUX 16 Ref (D55fb) BC2 (MC3 FB) : MUX 18 Ref (C36fb) TX_FLAG (MC14 FB) : MUX 19 Ref (D63fb) MD10 (MC22 P) : MUX 21 Ref (C40p) BC4 (MC4 FB) : MUX 22 Ref (C37fb) RX_FLAG (MC17 FB) : MUX 23 Ref (F92fb) BC1 (MC1 FB) : MUX 24 Ref (C33fb) MD9 (MC21 P) : MUX 25 Ref (C38p) BC3 (MC5 FB) : MUX 26 Ref (C38fb) RSR3 (MC16 FB) : MUX 28 Ref (F82fb) INIT (MC26 P) : MUX 30 Ref (D64p) RS10 (MC18 FB) : MUX 35 Ref (G107fb) FanIn assignment for block D [36] { BR_CLR, CLK, DATA9,DATA11,DATA10,DATA7,DATA8, INIT, LED0, MD7,MD4,MD3,MD6,MD5,MD8,MD10,MD11,MD9, OMNI_IO_PAUSE, RXA5,RXA4,RXA3,RXA1,RXA0,RXA2,RX_FLAG, TS10,TX_FLAG.AR,TS2,TP3,TX_FLAG, XXL_575,XXL_565,XXL_572,XXL_570,XXL_576, } Multiplexer assignment for block D MD7 (MC31 P) : MUX 0 Ref (E73p) TS10 (MC2 FB) : MUX 1 Ref (A16fb) TX_FLAG.AR (MC7 FB) : MUX 2 Ref (D52fb) RXA5 (MC20 P) : MUX 3 Ref (B24p) DATA9 (MC5 P) : MUX 4 Ref (C45p) MD4 (MC34 P) : MUX 5 Ref (F85p) MD3 (MC35 P) : MUX 6 Ref (F91p) TS2 (MC1 FB) : MUX 7 Ref (A10fb) LED0 (MC16 P) : MUX 8 Ref (H125p) TP3 (MC29 P) : MUX 9 Ref (D51p) CLK (MC36 P) : MUX 10 Ref (H128p) DATA11 (MC4 P) : MUX 11 Ref (B19p) XXL_575 (MC8 FB) : MUX 12 Ref (D54fb) DATA10 (MC3 P) : MUX 13 Ref (B17p) MD6 (MC33 P) : MUX 14 Ref (E80p) TX_FLAG (MC11 FB) : MUX 15 Ref (D63fb) RXA4 (MC21 P) : MUX 16 Ref (B25p) MD5 (MC32 P) : MUX 18 Ref (E77p) MD8 (MC24 P) : MUX 19 Ref (C37p) RXA3 (MC22 P) : MUX 20 Ref (B27p) MD10 (MC26 P) : MUX 21 Ref (C40p) XXL_565 (MC13 FB) : MUX 22 Ref (F87fb) DATA7 (MC12 P) : MUX 23 Ref (E69p) XXL_572 (MC10 FB) : MUX 25 Ref (D60fb) DATA8 (MC6 P) : MUX 26 Ref (C46p) RXA1 (MC19 P) : MUX 27 Ref (A6p) MD11 (MC27 P) : MUX 28 Ref (C43p) XXL_570 (MC14 FB) : MUX 29 Ref (F89fb) RXA0 (MC18 P) : MUX 31 Ref (A3p) RXA2 (MC23 P) : MUX 32 Ref (B29p) OMNI_IO_PAUSE (MC28 P) : MUX 33 Ref (D49p) XXL_576 (MC9 FB) : MUX 34 Ref (D55fb) MD9 (MC25 P) : MUX 35 Ref (C38p) RX_FLAG (MC15 FB) : MUX 37 Ref (F92fb) INIT (MC30 P) : MUX 38 Ref (D64p) BR_CLR (MC17 FB) : MUX 39 Ref (H127fb) FanIn assignment for block E [37] { Com_Ctrl_559, DATA4,DATA6,DATA5, INIT, MD11,MD9, OMNI_IO_PAUSE, RS1,RC2,RC0,RSR4,RSR6,RS10,RSR5,RC1,RSR7, TCK6,TCK8,TCK1,TS2,TCK0,TP3,TCK10,TCK4,TLC0,TCK5,TCK11,TCK3,TCK2,TCK7,TCK9,TCK13,TCK12, XXL_575,XXL_576,XXL_624, } Multiplexer assignment for block E TCK6 (MC3 FB) : MUX 0 Ref (B18fb) RS1 (MC31 FB) : MUX 1 Ref (G110fb) TCK8 (MC4 FB) : MUX 2 Ref (B20fb) Com_Ctrl_559 (MC10 FB) : MUX 3 Ref (B26fb) TCK1 (MC16 FB) : MUX 4 Ref (E66fb) RC2 (MC29 FB) : MUX 5 Ref (G105fb) DATA4 (MC22 P) : MUX 6 Ref (E75p) TS2 (MC1 FB) : MUX 7 Ref (A10fb) TCK0 (MC15 FB) : MUX 8 Ref (E65fb) RC0 (MC2 FB) : MUX 9 Ref (A14fb) MD11 (MC34 P) : MUX 10 Ref (C43p) DATA6 (MC17 P) : MUX 11 Ref (E67p) INIT (MC37 P) : MUX 12 Ref (D64p) TP3 (MC36 P) : MUX 13 Ref (D51p) TCK10 (MC7 FB) : MUX 14 Ref (B23fb) OMNI_IO_PAUSE (MC35 P) : MUX 15 Ref (D49p) TCK4 (MC21 FB) : MUX 17 Ref (E74fb) TLC0 (MC19 FB) : MUX 18 Ref (E71fb) XXL_575 (MC12 FB) : MUX 20 Ref (D54fb) TCK5 (MC23 FB) : MUX 21 Ref (E77fb) TCK11 (MC8 FB) : MUX 22 Ref (B24fb) TCK3 (MC24 FB) : MUX 23 Ref (E80fb) TCK2 (MC18 FB) : MUX 24 Ref (E68fb) MD9 (MC33 P) : MUX 25 Ref (C38p) RSR4 (MC27 FB) : MUX 26 Ref (G99fb) RSR6 (MC32 FB) : MUX 27 Ref (H128fb) TCK7 (MC5 FB) : MUX 28 Ref (B21fb) DATA5 (MC20 P) : MUX 29 Ref (E72p) TCK9 (MC6 FB) : MUX 30 Ref (B22fb) RS10 (MC30 FB) : MUX 31 Ref (G107fb) RSR5 (MC26 FB) : MUX 32 Ref (G97fb) TCK13 (MC11 FB) : MUX 33 Ref (B27fb) RC1 (MC28 FB) : MUX 34 Ref (G104fb) RSR7 (MC25 FB) : MUX 35 Ref (F90fb) TCK12 (MC9 FB) : MUX 37 Ref (B25fb) XXL_576 (MC13 FB) : MUX 38 Ref (D55fb) XXL_624 (MC14 FB) : MUX 39 Ref (D58fb) FanIn assignment for block F [37] { INIT, MD7,MD11,MD9,MD6, OMNI_IO_PAUSE, RS5,RXA0,RXA2,RX_FLAG.AR,RXA1,RS10,RS4,RS3,RS6, TCK5,TCK11,TS0,TCK6,TCK0,TLC1,TCK7,TCK3,TLC2,TCK10,TCK8,TCK12,TCK9,TLC0,TS2,TCK1,TCK4,TCK2,TCK13, UART_RX, XXL_575,XXL_624, } Multiplexer assignment for block F MD7 (MC36 P) : MUX 0 Ref (E73p) TCK5 (MC19 FB) : MUX 1 Ref (E77fb) RS5 (MC24 FB) : MUX 2 Ref (G103fb) UART_RX (MC30 P) : MUX 3 Ref (A8p) TCK11 (MC8 FB) : MUX 4 Ref (B24fb) TS0 (MC2 FB) : MUX 5 Ref (A15fb) TCK6 (MC3 FB) : MUX 6 Ref (B18fb) RXA0 (MC28 P) : MUX 7 Ref (A3p) TCK0 (MC14 FB) : MUX 8 Ref (E65fb) MD11 (MC33 P) : MUX 10 Ref (C43p) TLC1 (MC20 FB) : MUX 11 Ref (E79fb) TCK7 (MC5 FB) : MUX 12 Ref (B21fb) TCK3 (MC21 FB) : MUX 13 Ref (E80fb) RXA2 (MC31 P) : MUX 14 Ref (B29p) TLC2 (MC22 FB) : MUX 15 Ref (F96fb) XXL_575 (MC12 FB) : MUX 16 Ref (D54fb) MD9 (MC32 P) : MUX 17 Ref (C38p) TCK10 (MC7 FB) : MUX 18 Ref (B23fb) XXL_624 (MC13 FB) : MUX 19 Ref (D58fb) RX_FLAG.AR (MC11 FB) : MUX 21 Ref (C48fb) OMNI_IO_PAUSE (MC34 P) : MUX 23 Ref (D49p) TCK8 (MC4 FB) : MUX 24 Ref (B20fb) TCK12 (MC9 FB) : MUX 25 Ref (B25fb) TCK9 (MC6 FB) : MUX 26 Ref (B22fb) RXA1 (MC29 P) : MUX 27 Ref (A6p) TLC0 (MC17 FB) : MUX 28 Ref (E71fb) TS2 (MC1 FB) : MUX 29 Ref (A10fb) INIT (MC35 P) : MUX 30 Ref (D64p) RS10 (MC26 FB) : MUX 31 Ref (G107fb) MD6 (MC37 P) : MUX 32 Ref (E80p) RS4 (MC25 FB) : MUX 33 Ref (G106fb) TCK1 (MC15 FB) : MUX 34 Ref (E66fb) TCK4 (MC18 FB) : MUX 35 Ref (E74fb) TCK2 (MC16 FB) : MUX 36 Ref (E68fb) RS3 (MC27 FB) : MUX 37 Ref (G108fb) RS6 (MC23 FB) : MUX 38 Ref (G100fb) TCK13 (MC10 FB) : MUX 39 Ref (B27fb) FanIn assignment for block G [22] { CNTR_START, INIT, MD11,MD9, OMNI_IO_PAUSE, RS8,RC2,RS2,RS6,RS10,RS3,RS9,RS4,RC1,RS7,RS1,RS5,RS0,RC0, UART_RX, XXL_624,XXL_575, } Multiplexer assignment for block G XXL_624 (MC3 FB) : MUX 1 Ref (D58fb) RS8 (MC5 FB) : MUX 2 Ref (G98fb) UART_RX (MC18 P) : MUX 3 Ref (A8p) RC2 (MC10 FB) : MUX 5 Ref (G105fb) RS2 (MC16 FB) : MUX 7 Ref (G111fb) RS6 (MC6 FB) : MUX 8 Ref (G100fb) RS10 (MC12 FB) : MUX 9 Ref (G107fb) MD11 (MC20 P) : MUX 10 Ref (C43p) RS3 (MC13 FB) : MUX 11 Ref (G108fb) INIT (MC22 P) : MUX 12 Ref (D64p) RS9 (MC7 FB) : MUX 14 Ref (G102fb) RS4 (MC11 FB) : MUX 15 Ref (G106fb) RC1 (MC9 FB) : MUX 16 Ref (G104fb) CNTR_START (MC4 FB) : MUX 17 Ref (E78fb) RS7 (MC14 FB) : MUX 19 Ref (G109fb) XXL_575 (MC2 FB) : MUX 20 Ref (D54fb) RS1 (MC15 FB) : MUX 21 Ref (G110fb) RS5 (MC8 FB) : MUX 22 Ref (G103fb) OMNI_IO_PAUSE (MC21 P) : MUX 23 Ref (D49p) MD9 (MC19 P) : MUX 25 Ref (C38p) RS0 (MC17 FB) : MUX 27 Ref (G112fb) RC0 (MC1 FB) : MUX 39 Ref (A14fb) FanIn assignment for block H [36] { BC3,BC1,BC4,BC8,BC10,BC7,BC5,BC2,BC9,BC11,BC6,BC0, CLK, DATA11, INIT, MD11,MD10,MD9, OMNI_IO_PAUSE, RS2,RS9,RXA5,RLC2,RXA4,RLC1,RXA3,RLC3,RLC0, TLC2,TLC1,TLC3,TP3,TLC0,TS2, UART_RX, XXL_575, } Multiplexer assignment for block H MD11 (MC32 P) : MUX 0 Ref (C43p) RS2 (MC25 FB) : MUX 1 Ref (G111fb) BC3 (MC11 FB) : MUX 2 Ref (C38fb) UART_RX (MC26 P) : MUX 3 Ref (A8p) RS9 (MC24 FB) : MUX 4 Ref (G102fb) OMNI_IO_PAUSE (MC33 P) : MUX 5 Ref (D49p) BC1 (MC7 FB) : MUX 6 Ref (C33fb) TLC2 (MC23 FB) : MUX 7 Ref (F96fb) BC4 (MC10 FB) : MUX 8 Ref (C37fb) RXA5 (MC27 P) : MUX 9 Ref (B24p) MD10 (MC31 P) : MUX 11 Ref (C40p) INIT (MC35 P) : MUX 12 Ref (D64p) RLC2 (MC5 FB) : MUX 13 Ref (B30fb) RXA4 (MC28 P) : MUX 14 Ref (B25p) BC8 (MC15 FB) : MUX 15 Ref (C42fb) XXL_575 (MC19 FB) : MUX 16 Ref (D54fb) TLC1 (MC21 FB) : MUX 17 Ref (E79fb) BC10 (MC17 FB) : MUX 19 Ref (C44fb) BC7 (MC13 FB) : MUX 20 Ref (C40fb) BC5 (MC14 FB) : MUX 21 Ref (C41fb) DATA11 (MC2 FB) : MUX 22 Ref (B19fb) RLC1 (MC4 FB) : MUX 23 Ref (B29fb) RXA3 (MC29 P) : MUX 24 Ref (B27p) RLC3 (MC6 FB) : MUX 25 Ref (B31fb) BC2 (MC9 FB) : MUX 26 Ref (C36fb) BC9 (MC16 FB) : MUX 27 Ref (C43fb) TLC3 (MC22 FB) : MUX 29 Ref (F95fb) TP3 (MC34 P) : MUX 31 Ref (D51p) CLK (MC36 P) : MUX 32 Ref (H128p) BC11 (MC18 FB) : MUX 33 Ref (C47fb) BC6 (MC12 FB) : MUX 34 Ref (C39fb) MD9 (MC30 P) : MUX 35 Ref (C38p) BC0 (MC8 FB) : MUX 36 Ref (C34fb) RLC0 (MC3 FB) : MUX 37 Ref (B28fb) TLC0 (MC20 FB) : MUX 38 Ref (E71fb) TS2 (MC1 FB) : MUX 39 Ref (A10fb) Creating JEDEC file C:\USERS\MALCOLM\ONEDRIVE\OMNIBUS-SERIAL-BOARD\CUPL-FILES\MAIN.jed ... PLCC84 programmed logic: ----------------------------------- BC0.T = 1; BC1.T = BC0.Q; BC2.T = (BC0.Q & BC1.Q); BC3.T = (BC0.Q & BC1.Q & BC2.Q); BC4.T = (BC0.Q & BC1.Q & BC2.Q & BC3.Q); BC5.T = (BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q); BC6.T = (BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q); BC7.T = (BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q & BC6.Q); BC8.T = (BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q & BC6.Q & BC7.Q); BC9.T = (BC8.Q & BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q & BC6.Q & BC7.Q); BC10.T = (BC9.Q & BC8.Q & BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q & BC6.Q & BC7.Q); BC11.T = (BC10.Q & BC9.Q & BC8.Q & BC0.Q & BC1.Q & BC2.Q & BC3.Q & BC4.Q & BC5.Q & BC6.Q & BC7.Q); BR_CLR.D = ((!BC10.Q & BC0.Q & !BC11.Q & BC1.Q & BC2.Q & BC4.Q & !BC7.Q & !BC9.Q & RXA3 & BC3.Q & BC5.Q & BC6.Q & BC8.Q & !RXA4 & RXA5) # (!BC10.Q & BC0.Q & !BC11.Q & BC1.Q & BC2.Q & BC4.Q & BC7.Q & !BC9.Q & !RXA3 & BC3.Q & BC5.Q & !BC6.Q & !BC8.Q & !RXA4 & RXA5) # (!BC10.Q & BC0.Q & !BC11.Q & BC1.Q & BC2.Q & BC4.Q & BC7.Q & BC9.Q & !RXA3 & BC3.Q & BC5.Q & BC6.Q & !BC8.Q & RXA4 & RXA5) # (!BC10.Q & BC0.Q & !BC11.Q & !BC1.Q & BC2.Q & !BC4.Q & !BC7.Q & !BC9.Q & !RXA3 & !BC3.Q & !BC5.Q & !BC6.Q & !BC8.Q & RXA4 & !RXA5) # (!BC10.Q & BC0.Q & !BC11.Q & !BC1.Q & !BC2.Q & !BC4.Q & !BC7.Q & !BC9.Q & RXA3 & !BC3.Q & !BC5.Q & !BC6.Q & !BC8.Q & !RXA4 & !RXA5) # (!BC10.Q & !BC0.Q & BC11.Q & BC1.Q & BC2.Q & !BC4.Q & !BC7.Q & !BC9.Q & RXA3 & BC3.Q & BC5.Q & !BC6.Q & !BC8.Q & RXA4 & RXA5) # (!BC10.Q & BC0.Q & !BC11.Q & BC1.Q & BC2.Q & BC4.Q & !BC7.Q & !BC9.Q & RXA3 & !BC3.Q & !BC5.Q & !BC6.Q & !BC8.Q & RXA4 & !RXA5)); !C0 = (!MD10 & MD11 & !OMNI_IO_PAUSE & XXL_575); CNTR_START.D = (RS1.Q & !RC0.Q & !RC1.Q & RC2.Q); !C1 = ((MD11 & !OMNI_IO_PAUSE & XXL_575 & !MD10) # (MD11 & !OMNI_IO_PAUSE & XXL_575 & !MD9)); DATA0.D = 1; DATA1.D = 1; DATA2.D = 1; DATA3.D = 1; DATA5.D = !RSR6.Q; DATA4.D = !RSR7.Q; DATA6.D = !RSR5.Q; DATA7.D = !RSR4.Q; DATA8.D = !RSR3.Q; DATA9.D = !RSR2.Q; DATA10.D = !RSR1.Q; !INTERNAL_IO = ((!OMNI_IO_PAUSE & MD4 & MD3 & !RXA0 & !MD8 & MD5 & MD6 & !MD7 & RXA1 & RXA2) # (!OMNI_IO_PAUSE & MD4 & !MD3 & MD5 & XXL_565 & XXL_570) # (!OMNI_IO_PAUSE & !MD4 & MD3 & RXA0 & !MD5 & !MD6 & MD7 & !RXA1 & !RXA2) # (!OMNI_IO_PAUSE & MD4 & MD3 & !RXA0 & !MD8 & !MD5 & MD6 & MD7 & !RXA1 & !RXA2) # (!OMNI_IO_PAUSE & MD4 & MD3 & !RXA0 & MD8 & XXL_572)); DATA11.D = !RSR0.Q; LED0.D = !DATA11.PIN; LED1.D = 0; INT_RQST = (!LED0.Q # (!RX_FLAG.Q & !TX_FLAG.Q)); LED2.D = 0; RC0.T = 1; RC1.T = RC0.Q; RC2.T = (RC0.Q & RC1.Q); RDRRUN.D = 0; RLC0.T = 1; RLC1.T = RLC0.Q; RLC2.T = (RLC0.Q & RLC1.Q); RLC3.T = (RLC0.Q & RLC1.Q & RLC2.Q); RS1.D = ((!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS0.Q & !RS1.Q & !UART_RX) # (!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS0.Q & XXL_579 & RS1.Q & !UART_RX)); RS0.D = ((!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS1.Q & !RS10.Q & !RS0.Q) # (!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & UART_RX & !RS0.Q) # (!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS1.Q & !RS0.Q & RC0.Q & RC1.Q & RC2.Q) # (!RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS1.Q & !RS10.Q & UART_RX)); RS3.D = ((!RS0.Q & !RS1.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS2.Q & RS3.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS2.Q & !RS3.Q & RC0.Q & RC1.Q & RC2.Q)); RS2.D = ((!RS0.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS1.Q & !RS2.Q & !RC0.Q & !RC1.Q & RC2.Q) # (!RS0.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS1.Q & RS2.Q & XXL_569)); RS4.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS3.Q & RS4.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS3.Q & !RS4.Q & RC0.Q & RC1.Q & RC2.Q)); RS5.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS4.Q & RS5.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS4.Q & !RS5.Q & RC0.Q & RC1.Q & RC2.Q)); RS8.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS9.Q & !RS10.Q & !RS7.Q & RS8.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS9.Q & !RS10.Q & RS7.Q & !RS8.Q & RC0.Q & RC1.Q & RC2.Q)); RS6.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS5.Q & RS6.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS7.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS5.Q & !RS6.Q & RC0.Q & RC1.Q & RC2.Q)); RS7.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS8.Q & !RS9.Q & !RS10.Q & !RS6.Q & RS7.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS8.Q & !RS9.Q & !RS10.Q & RS6.Q & !RS7.Q & RC0.Q & RC1.Q & RC2.Q)); RS9.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS10.Q & !RS8.Q & RS9.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS10.Q & RS8.Q & !RS9.Q & RC0.Q & RC1.Q & RC2.Q)); RS10.D = ((!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & !RS9.Q & RS10.Q & XXL_569) # (!RS0.Q & !RS1.Q & !RS2.Q & !RS3.Q & !RS4.Q & !RS5.Q & !RS6.Q & !RS7.Q & !RS8.Q & RS9.Q & !RS10.Q & RC0.Q & RC1.Q & RC2.Q)); RSR0.D = UART_RX; RSR2.D = UART_RX; RSR1.D = UART_RX; RSR3.D = UART_RX; RSR4.D = UART_RX; RSR5.D = UART_RX; RSR6.D = UART_RX; RSR7.D = UART_RX; STROBE.D = 0; RX_FLAG.D = 1; !SKIP = ((MD10 & !MD11 & !OMNI_IO_PAUSE & XXL_576 & LED0.Q & TX_FLAG.Q) # (MD10 & !MD11 & !OMNI_IO_PAUSE & XXL_576 & MD9 & TX_FLAG.Q) # (MD10 & !MD11 & !OMNI_IO_PAUSE & MD9 & RX_FLAG.Q & XXL_575) # (MD10 & !MD11 & !OMNI_IO_PAUSE & XXL_576 & LED0.Q & !MD9 & RX_FLAG.Q)); TC0.T = 1; TC1.T = TC0.Q; TC2.T = (TC0.Q & TC1.Q); TCK0.T = 1; TCK1.T = TCK0.Q; TCK2.T = (TCK0.Q & TCK1.Q); TCK3.T = (TCK0.Q & TCK1.Q & TCK2.Q); TCK4.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q); TCK5.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q); TCK6.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q); TCK7.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q); TCK8.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q); TCK9.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q & TCK8.Q); TCK10.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q & TCK8.Q & TCK9.Q); TCK11.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q & TCK8.Q & TCK9.Q & TCK10.Q); TCK12.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q & TCK8.Q & TCK9.Q & TCK10.Q & TCK11.Q); TCK13.T = (TCK0.Q & TCK1.Q & TCK2.Q & TCK3.Q & TCK4.Q & TCK5.Q & TCK6.Q & TCK7.Q & TCK8.Q & TCK9.Q & TCK10.Q & TCK11.Q & TCK12.Q); TLC0.T = 1; TLC1.T = TLC0.Q; TLC2.T = (TLC0.Q & TLC1.Q); TLC3.T = (TLC0.Q & TLC1.Q & TLC2.Q); TS0.D = ((!TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS0.Q & TC0.Q & !TC1.Q & TC2.Q) # (!TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !STROBE.Q) # (!TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS0.Q)); TS2.D = ((!TS0.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS1.Q & TS2.Q & XXL_568) # (!TS0.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS1.Q & !TS2.Q & TC0.Q & TC1.Q & TC2.Q)); TS1.D = ((!TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS1.Q & !TS0.Q & XXL_568) # (!TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS1.Q & STROBE.Q & TS0.Q)); TS3.D = ((!TS0.Q & !TS1.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS2.Q & TS3.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS2.Q & !TS3.Q & TC0.Q & TC1.Q & TC2.Q)); TS5.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS4.Q & TS5.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS4.Q & !TS5.Q & TC0.Q & TC1.Q & TC2.Q)); TS4.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS3.Q & TS4.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS3.Q & !TS4.Q & TC0.Q & TC1.Q & TC2.Q)); TS6.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS5.Q & TS6.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS7.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS5.Q & !TS6.Q & TC0.Q & TC1.Q & TC2.Q)); TS7.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS8.Q & !TS9.Q & !TS10.Q & !TS6.Q & TS7.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS8.Q & !TS9.Q & !TS10.Q & TS6.Q & !TS7.Q & TC0.Q & TC1.Q & TC2.Q)); TS9.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS10.Q & !TS8.Q & TS9.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS10.Q & TS8.Q & !TS9.Q & TC0.Q & TC1.Q & TC2.Q)); TS8.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS9.Q & !TS10.Q & !TS7.Q & TS8.Q & XXL_568) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS9.Q & !TS10.Q & TS7.Q & !TS8.Q & TC0.Q & TC1.Q & TC2.Q)); TS10.D = ((!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & !TS9.Q & TS10.Q & XXL_580) # (!TS0.Q & !TS1.Q & !TS2.Q & !TS3.Q & !TS4.Q & !TS5.Q & !TS6.Q & !TS7.Q & !TS8.Q & TS9.Q & !TS10.Q & TC0.Q & TC1.Q & TC2.Q)); TSR0.D = !DATA11.PIN; TSR1.D = !DATA10.PIN; TSR3.D = !DATA8.PIN; TSR2.D = !DATA9.PIN; TSR4.D = !DATA7.PIN; TSR5.D = !DATA6.PIN; TSR6.D = !DATA5.PIN; TX_FLAG.D = 1; TSR7.D = !DATA4.PIN; UART_TX = ((TS4.Q & TSR2.Q) # (TS5.Q & TSR3.Q) # (TS6.Q & TSR4.Q) # (TS7.Q & TSR5.Q) # (TS8.Q & TSR6.Q) # (TS9.Q & TSR7.Q) # (TS2.Q & TSR0.Q) # TS0.Q # TS10.Q # (TS3.Q & TSR1.Q)); !Com_Ctrl_558 = (!INIT & !TS2.Q); Com_Ctrl_559 = (INIT # (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & TCK12.Q & TCK13.Q)); !Com_Ctrl_560 = (!INIT & !RS2.Q); !Com_Ctrl_561 = (!CNTR_START.Q & !RS0.Q); !Com_Ctrl_562 = (!BR_CLR.Q & !INIT); XXL_565 = ((MD7 & RXA0) # (!MD7 & !RXA0)); !XXL_568 = (TC0.Q & TC1.Q & TC2.Q); !XXL_569 = (RC0.Q & RC1.Q & RC2.Q); XXL_570 = ((MD6 & !RXA1 & RXA2) # (!MD6 & RXA1 & !RXA2)); XXL_572 = ((MD5 & !MD6 & MD7 & RXA1 & RXA2) # (!MD5 & MD6 & !MD7 & !RXA1 & !RXA2)); XXL_575 = ((MD4 & MD5 & MD3 & !MD8 & MD6 & !MD7 & !RXA0 & RXA1 & RXA2) # (!MD4 & !MD5 & MD3 & MD8 & !MD6 & MD7 & RXA0 & !RXA1 & !RXA2) # (MD4 & !MD5 & MD3 & !MD8 & MD6 & MD7 & !RXA0 & !RXA1 & !RXA2) # (MD4 & MD5 & !MD3 & MD8 & XXL_565 & XXL_570)); XXL_576 = ((MD3 & !MD4 & !MD8 & RXA0 & !MD5 & !MD6 & MD7 & !RXA1 & !RXA2) # (!MD3 & MD4 & !MD8 & MD5 & XXL_565 & XXL_570) # (MD3 & MD4 & MD8 & !RXA0 & XXL_572)); !XXL_579 = (!RC0.Q & !RC1.Q & RC2.Q); !XXL_580 = (TC0.Q & !TC1.Q & TC2.Q); !XXL_609 = (!RXA3 & !RXA4 & !RXA5); XXL_624 = ((BR_CLR.Q & XXL_609) # (CLK & !RXA3 & !RXA4 & !RXA5)); BC0.C = CLK; BC0.AR = Com_Ctrl_562; BC1.C = CLK; BC1.AR = Com_Ctrl_562; BC2.C = CLK; BC2.AR = Com_Ctrl_562; BC3.C = CLK; BC3.AR = Com_Ctrl_562; BC4.C = CLK; BC4.AR = Com_Ctrl_562; BC5.C = CLK; BC5.AR = Com_Ctrl_562; BC6.C = CLK; BC6.AR = Com_Ctrl_562; BC7.C = CLK; BC7.AR = Com_Ctrl_562; BC8.C = CLK; BC8.AR = Com_Ctrl_562; BC9.C = CLK; BC9.AR = Com_Ctrl_562; BC10.C = CLK; BC10.AR = Com_Ctrl_562; BC11.C = CLK; BC11.AR = Com_Ctrl_562; BR_CLR.C = !CLK; BR_CLR.AR = INIT; CNTR_START.C = XXL_624; CNTR_START.AR = INIT; DATA0.C = !RS10.Q; DATA0.AR = INIT; DATA0.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA1.C = !RS10.Q; DATA1.AR = INIT; DATA1.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA2.C = !RS10.Q; DATA2.AR = INIT; DATA2.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA3.C = !RS10.Q; DATA3.AR = INIT; DATA3.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA5.C = !RS10.Q; DATA5.AR = INIT; DATA5.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA4.C = !RS10.Q; DATA4.AR = INIT; DATA4.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA6.C = !RS10.Q; DATA6.AR = INIT; DATA6.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA7.C = !RS10.Q; DATA7.AR = INIT; DATA7.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA8.C = !RS10.Q; DATA8.AR = INIT; DATA8.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA9.C = !RS10.Q; DATA9.AR = INIT; DATA9.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA10.C = !RS10.Q; DATA10.AR = INIT; DATA10.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); DATA11.C = !RS10.Q; DATA11.AR = INIT; DATA11.OE = (!MD9 & MD11 & !OMNI_IO_PAUSE & XXL_575); LED0.C = (!MD11 & !OMNI_IO_PAUSE & TP3 & XXL_575 & !MD9 & MD10); LED0.AP = INIT; LED1.C = (TLC0.Q & TLC1.Q & TLC2.Q & TLC3.Q); LED1.AR = INIT; LED1.AP = TS2.Q; LED2.C = (RLC0.Q & RLC1.Q & RLC2.Q & RLC3.Q); LED2.AR = INIT; LED2.AP = RS2.Q; RC0.C = !XXL_624; RC0.AR = Com_Ctrl_561; RC1.C = !XXL_624; RC1.AR = Com_Ctrl_561; RC2.C = !XXL_624; RC2.AR = Com_Ctrl_561; RDRRUN.C = RS2.Q; RDRRUN.AR = INIT; RDRRUN.AP = (!MD10 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_575); RLC0.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); RLC0.AR = Com_Ctrl_560; RLC1.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); RLC1.AR = Com_Ctrl_560; RLC2.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); RLC2.AR = Com_Ctrl_560; RLC3.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); RLC3.AR = Com_Ctrl_560; RS1.C = XXL_624; RS0.C = XXL_624; RS3.C = XXL_624; RS2.C = XXL_624; RS4.C = XXL_624; RS5.C = XXL_624; RS8.C = XXL_624; RS6.C = XXL_624; RS7.C = XXL_624; RS9.C = XXL_624; RS10.C = XXL_624; RSR0.C = RS3.Q; RSR2.C = RS5.Q; RSR1.C = RS4.Q; RSR3.C = RS6.Q; RSR4.C = RS7.Q; RSR5.C = RS8.Q; RSR6.C = RS9.Q; RSR7.C = RS10.Q; STROBE.C = TS2.Q; STROBE.AR = INIT; STROBE.AP = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); RX_FLAG.C = !RS10.Q; RX_FLAG.AR = ((MD11 & !OMNI_IO_PAUSE & TP3 & XXL_575 & !MD10) # INIT # (MD11 & !OMNI_IO_PAUSE & TP3 & XXL_575 & MD9)); TC0.C = XXL_624; TC0.AR = TS0.Q; TC1.C = XXL_624; TC1.AR = TS0.Q; TC2.C = XXL_624; TC2.AR = TS0.Q; TCK0.C = CLK; TCK0.AR = Com_Ctrl_559; TCK1.C = CLK; TCK1.AR = Com_Ctrl_559; TCK2.C = CLK; TCK2.AR = Com_Ctrl_559; TCK3.C = CLK; TCK3.AR = Com_Ctrl_559; TCK4.C = CLK; TCK4.AR = Com_Ctrl_559; TCK5.C = CLK; TCK5.AR = Com_Ctrl_559; TCK6.C = CLK; TCK6.AR = Com_Ctrl_559; TCK7.C = CLK; TCK7.AR = Com_Ctrl_559; TCK8.C = CLK; TCK8.AR = Com_Ctrl_559; TCK9.C = CLK; TCK9.AR = Com_Ctrl_559; TCK10.C = CLK; TCK10.AR = Com_Ctrl_559; TCK11.C = CLK; TCK11.AR = Com_Ctrl_559; TCK12.C = CLK; TCK12.AR = Com_Ctrl_559; TCK13.C = CLK; TCK13.AR = Com_Ctrl_559; TLC0.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); TLC0.AR = Com_Ctrl_558; TLC1.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); TLC1.AR = Com_Ctrl_558; TLC2.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); TLC2.AR = Com_Ctrl_558; TLC3.C = (!TCK0.Q & !TCK1.Q & !TCK2.Q & !TCK3.Q & !TCK4.Q & !TCK5.Q & !TCK6.Q & !TCK7.Q & !TCK8.Q & !TCK9.Q & !TCK10.Q & !TCK11.Q & !TCK12.Q & !TCK13.Q); TLC3.AR = Com_Ctrl_558; TS0.C = XXL_624; TS2.C = XXL_624; TS1.C = XXL_624; TS3.C = XXL_624; TS5.C = XXL_624; TS4.C = XXL_624; TS6.C = XXL_624; TS7.C = XXL_624; TS9.C = XXL_624; TS8.C = XXL_624; TS10.C = XXL_624; TSR0.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR1.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR3.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR2.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR4.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR5.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TSR6.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); TX_FLAG.C = TS10.Q; TX_FLAG.AR = (INIT # (!MD10 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576)); TX_FLAG.AP = (MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576 & MD9 & MD10); TSR7.C = (!MD9 & MD11 & !OMNI_IO_PAUSE & TP3 & XXL_576); PLCC84 Pin/Node Placement: ------------------------------------ Pin 9 = UART_RX; /* MC 8 */ Pin 10 = RXA1; /* MC 6 */ Pin 11 = UART_TX; /* MC 5 */ Pin 12 = RXA0; /* MC 3 */ Pin 14 = TDI; /* MC 32 */ Pin 15 = RXA2; /* MC 29 */ Pin 16 = RXA3; /* MC 27 */ Pin 17 = RXA4; /* MC 25 */ Pin 18 = RXA5; /* MC 24 */ Pin 21 = DATA11; /* MC 19 */ Pin 22 = DATA10; /* MC 17 */ Pin 23 = TMS; /* MC 48 */ Pin 24 = DATA8; /* MC 46 */ Pin 25 = DATA9; /* MC 45 */ Pin 27 = MD11; /* MC 43 */ Pin 28 = MD10; /* MC 40 */ Pin 29 = MD9; /* MC 38 */ Pin 30 = MD8; /* MC 37 */ Pin 31 = SKIP; /* MC 35 */ Pin 33 = INIT; /* MC 64 */ Pin 34 = INT_RQST; /* MC 61 */ Pin 36 = INTERNAL_IO; /* MC 57 */ Pin 37 = C1; /* MC 56 */ Pin 39 = C0; /* MC 53 */ Pin 40 = TP3; /* MC 51 */ Pin 41 = OMNI_IO_PAUSE; /* MC 49 */ Pin 45 = DATA6; /* MC 67 */ Pin 46 = DATA7; /* MC 69 */ Pin 48 = DATA5; /* MC 72 */ Pin 49 = MD7; /* MC 73 */ Pin 50 = DATA4; /* MC 75 */ Pin 51 = MD5; /* MC 77 */ Pin 52 = MD6; /* MC 80 */ Pin 54 = DATA3; /* MC 83 */ Pin 55 = MD4; /* MC 85 */ Pin 56 = DATA1; /* MC 86 */ Pin 57 = DATA2; /* MC 88 */ Pin 58 = MD3; /* MC 91 */ Pin 62 = TCK; /* MC 96 */ Pin 65 = DATA0; /* MC 101 */ Pin 71 = TDO; /* MC 112 */ Pin 75 = LED1; /* MC 118 */ Pin 77 = LED2; /* MC 123 */ Pin 79 = LED0; /* MC 125 */ Pin 81 = CLK; /* MC 128 */ PINNODE 314 = XXL_580; /* MC 14 Foldback */ PINNODE 315 = XXL_568; /* MC 15 Foldback */ PINNODE 316 = Com_Ctrl_561; /* MC 16 Foldback */ PINNODE 332 = Com_Ctrl_560; /* MC 32 Foldback */ PINNODE 348 = Com_Ctrl_562; /* MC 48 Foldback */ PINNODE 354 = XXL_609; /* MC 54 Foldback */ PINNODE 371 = Com_Ctrl_558; /* MC 71 Foldback */ PINNODE 396 = Com_Ctrl_558; /* MC 96 Foldback */ PINNODE 402 = XXL_579; /* MC 102 Foldback */ PINNODE 410 = XXL_569; /* MC 110 Foldback */ PINNODE 411 = Com_Ctrl_561; /* MC 111 Foldback */ PINNODE 601 = TS9; /* MC 1 Feedback */ PINNODE 602 = TS8; /* MC 2 Feedback */ PINNODE 603 = TS7; /* MC 3 Feedback */ PINNODE 606 = TS6; /* MC 6 Feedback */ PINNODE 607 = TS5; /* MC 7 Feedback */ PINNODE 608 = TS4; /* MC 8 Feedback */ PINNODE 609 = TS3; /* MC 9 Feedback */ PINNODE 610 = TS2; /* MC 10 Feedback */ PINNODE 611 = TC1; /* MC 11 Feedback */ PINNODE 612 = TS1; /* MC 12 Feedback */ PINNODE 613 = TC2; /* MC 13 Feedback */ PINNODE 614 = RC0; /* MC 14 Feedback */ PINNODE 615 = TS0; /* MC 15 Feedback */ PINNODE 616 = TS10; /* MC 16 Feedback */ PINNODE 618 = TCK6; /* MC 18 Feedback */ PINNODE 620 = TCK8; /* MC 20 Feedback */ PINNODE 621 = TCK7; /* MC 21 Feedback */ PINNODE 622 = TCK9; /* MC 22 Feedback */ PINNODE 623 = TCK10; /* MC 23 Feedback */ PINNODE 624 = TCK11; /* MC 24 Feedback */ PINNODE 625 = TCK12; /* MC 25 Feedback */ PINNODE 626 = Com_Ctrl_559; /* MC 26 Feedback */ PINNODE 627 = TCK13; /* MC 27 Feedback */ PINNODE 628 = RLC0; /* MC 28 Feedback */ PINNODE 629 = RLC1; /* MC 29 Feedback */ PINNODE 630 = RLC2; /* MC 30 Feedback */ PINNODE 631 = RLC3; /* MC 31 Feedback */ PINNODE 632 = RDRRUN; /* MC 32 Feedback */ PINNODE 633 = BC1; /* MC 33 Feedback */ PINNODE 634 = BC0; /* MC 34 Feedback */ PINNODE 636 = BC2; /* MC 36 Feedback */ PINNODE 637 = BC4; /* MC 37 Feedback */ PINNODE 638 = BC3; /* MC 38 Feedback */ PINNODE 639 = BC6; /* MC 39 Feedback */ PINNODE 640 = BC7; /* MC 40 Feedback */ PINNODE 641 = BC5; /* MC 41 Feedback */ PINNODE 642 = BC8; /* MC 42 Feedback */ PINNODE 643 = BC9; /* MC 43 Feedback */ PINNODE 644 = BC10; /* MC 44 Feedback */ PINNODE 647 = BC11; /* MC 47 Feedback */ PINNODE 648 = RX_FLAG.AR; /* MC 48 Feedback */ PINNODE 649 = TSR4; /* MC 49 Feedback */ PINNODE 650 = TSR2; /* MC 50 Feedback */ PINNODE 651 = TSR1; /* MC 51 Feedback */ PINNODE 652 = TX_FLAG.AR; /* MC 52 Feedback */ PINNODE 654 = XXL_575; /* MC 54 Feedback */ PINNODE 655 = XXL_576; /* MC 55 Feedback */ PINNODE 658 = XXL_624; /* MC 58 Feedback */ PINNODE 659 = TSR3; /* MC 59 Feedback */ PINNODE 660 = XXL_572; /* MC 60 Feedback */ PINNODE 662 = STROBE; /* MC 62 Feedback */ PINNODE 663 = TX_FLAG; /* MC 63 Feedback */ PINNODE 664 = TSR0; /* MC 64 Feedback */ PINNODE 665 = TCK0; /* MC 65 Feedback */ PINNODE 666 = TCK1; /* MC 66 Feedback */ PINNODE 668 = TCK2; /* MC 68 Feedback */ PINNODE 670 = TSR5; /* MC 70 Feedback */ PINNODE 671 = TLC0; /* MC 71 Feedback */ PINNODE 673 = TSR6; /* MC 73 Feedback */ PINNODE 674 = TCK4; /* MC 74 Feedback */ PINNODE 676 = TSR7; /* MC 76 Feedback */ PINNODE 677 = TCK5; /* MC 77 Feedback */ PINNODE 678 = CNTR_START; /* MC 78 Feedback */ PINNODE 679 = TLC1; /* MC 79 Feedback */ PINNODE 680 = TCK3; /* MC 80 Feedback */ PINNODE 681 = RSR2; /* MC 81 Feedback */ PINNODE 682 = RSR3; /* MC 82 Feedback */ PINNODE 684 = RSR1; /* MC 84 Feedback */ PINNODE 685 = RSR0; /* MC 85 Feedback */ PINNODE 687 = XXL_565; /* MC 87 Feedback */ PINNODE 689 = XXL_570; /* MC 89 Feedback */ PINNODE 690 = RSR7; /* MC 90 Feedback */ PINNODE 691 = TC0; /* MC 91 Feedback */ PINNODE 692 = RX_FLAG; /* MC 92 Feedback */ PINNODE 695 = TLC3; /* MC 95 Feedback */ PINNODE 696 = TLC2; /* MC 96 Feedback */ PINNODE 697 = RSR5; /* MC 97 Feedback */ PINNODE 698 = RS8; /* MC 98 Feedback */ PINNODE 699 = RSR4; /* MC 99 Feedback */ PINNODE 700 = RS6; /* MC 100 Feedback */ PINNODE 702 = RS9; /* MC 102 Feedback */ PINNODE 703 = RS5; /* MC 103 Feedback */ PINNODE 704 = RC1; /* MC 104 Feedback */ PINNODE 705 = RC2; /* MC 105 Feedback */ PINNODE 706 = RS4; /* MC 106 Feedback */ PINNODE 707 = RS10; /* MC 107 Feedback */ PINNODE 708 = RS3; /* MC 108 Feedback */ PINNODE 709 = RS7; /* MC 109 Feedback */ PINNODE 710 = RS1; /* MC 110 Feedback */ PINNODE 711 = RS2; /* MC 111 Feedback */ PINNODE 712 = RS0; /* MC 112 Feedback */ PINNODE 727 = BR_CLR; /* MC 127 Feedback */ PINNODE 728 = RSR6; /* MC 128 Feedback */ ** Resource Usage ** DCERP Field = Summary of Allocations. ||||| |||||_Preset [p,-] == p = PT preset, - No Preset. |||| ||||__Reset [g,r,-] == g= Global AR, r = PT reset, - No reset. ||| |||___Clock Enable [e,-] == e = Product Term, - always enabled, - none. || ||____Clock [c,g,-], == c = Product term, g = Global term, - No Clock. | |_____Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff. For input only = INPUT. MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT output_slew MC1 0 -- TS9 Dc--- -- -- 3 slow MC2 0 -- TS8 Dc--- -- -- 3 slow MC3 12 -- RXA0 INPUT TS7 Dc--- -- -- 3 slow MC4 0 -- -- NA -> UART_TX 5 slow MC5 11 on UART_TX C---- -- NA -- 5 slow MC6 10 -- RXA1 INPUT TS6 Dc--- -- -- 3 slow MC7 0 -- TS5 Dc--- -- -- 3 slow MC8 9 -- UART_RX INPUT TS4 Dc--- -- -- 3 slow MC9 0 -- TS3 Dc--- -- -- 3 slow MC10 0 -- TS2 Dc--- -- -- 3 slow MC11 8 -- TC1 Tc-r- -- -- 3 slow MC12 0 -- TS1 Dc--- -- -- 3 slow MC13 6 -- TC2 Tc-r- -- -- 3 slow MC14 5 -- RC0 Tc-r- XXL_580 -- 3 slow MC15 0 -- TS0 Dc--- XXL_568 -- 5 slow MC16 4 -- TS10 Dc--- Com_Ctrl_561 -- 4 slow MC17 22 PT DATA10 Dc-r- -- -- -- 4 slow MC18 0 -- TCK6 Tg-r- -- -- 2 slow MC19 21 PT DATA11 Dc-r- -- -- -- 4 slow MC20 0 -- TCK8 Tg-r- -- -- 2 slow MC21 20 -- TCK7 Tg-r- -- -- 2 slow MC22 0 -- TCK9 Tg-r- -- -- 2 slow MC23 0 -- TCK10 Tg-r- -- -- 2 slow MC24 18 -- RXA5 INPUT TCK11 Tg-r- -- -- 2 slow MC25 17 -- RXA4 INPUT TCK12 Tg-r- -- -- 2 slow MC26 0 -- Com_Ctrl_559 C---- -- -- 2 slow MC27 16 -- RXA3 INPUT TCK13 Tg-r- -- -- 2 slow MC28 0 -- RLC0 Tc-r- -- -- 2 slow MC29 15 -- RXA2 INPUT RLC1 Tc-r- -- -- 3 slow MC30 0 -- RLC2 Tc-r- -- -- 3 slow MC31 0 -- RLC3 Tc-r- -- -- 3 slow MC32 14 -- TDI INPUT RDRRUN Dc-rp Com_Ctrl_560 -- 4 slow MC33 0 -- BC1 Tg-r- -- -- 2 slow MC34 0 -- BC0 Tg-r- -- -- 1 slow MC35 31 on SKIP C---- -- -- -- 4 slow MC36 0 -- BC2 Tg-r- -- -- 2 slow MC37 30 -- MD8 INPUT BC4 Tg-r- -- -- 2 slow MC38 29 -- MD9 INPUT BC3 Tg-r- -- -- 2 slow MC39 0 -- BC6 Tg-r- -- -- 2 slow MC40 28 -- MD10 INPUT BC7 Tg-r- -- -- 2 slow MC41 0 -- BC5 Tg-r- -- -- 2 slow MC42 0 -- BC8 Tg-r- -- -- 2 slow MC43 27 -- MD11 INPUT BC9 Tg-r- -- -- 2 slow MC44 0 -- BC10 Tg-r- -- -- 2 slow MC45 25 PT DATA9 Dc-r- -- -- -- 4 slow MC46 24 PT DATA8 Dc-r- -- -- -- 4 slow MC47 0 -- BC11 Tg-r- -- -- 2 slow MC48 23 -- TMS INPUT RX_FLAG.AR C---- Com_Ctrl_562 -- 4 slow MC49 41 -- OMNI_IO_PAUSE INPUT TSR4 Dc--- -- -- 2 slow MC50 0 -- TSR2 Dc--- -- -- 2 slow MC51 40 -- TP3 INPUT TSR1 Dc--- -- -- 2 slow MC52 0 -- TX_FLAG.AR C---- -- -- 2 slow MC53 39 on C0 C---- -- -- -- 1 slow MC54 0 -- XXL_575 C---- XXL_609 -- 5 slow MC55 0 -- XXL_576 C---- -- -- 3 slow MC56 37 on C1 C---- -- -- -- 2 slow MC57 36 on INTERNAL_IO C---- -- NA -- 5 slow MC58 0 -- XXL_624 C---- -- -- 2 slow MC59 35 -- TSR3 Dc--- -- -- 2 slow MC60 0 -- XXL_572 C---- -- -- 2 slow MC61 34 on INT_RQST C---- -- -- -- 2 slow MC62 0 -- STROBE Dc-rp -- -- 3 slow MC63 0 -- TX_FLAG Dc-rp -- -- 3 slow MC64 33 -- INIT INPUT TSR0 Dc--- -- -- 2 slow MC65 44 -- TCK0 Tg-r- -- -- 1 slow MC66 0 -- TCK1 Tg-r- -- -- 2 slow MC67 45 PT DATA6 Dc-r- -- -- -- 4 slow MC68 0 -- TCK2 Tg-r- -- -- 2 slow MC69 46 PT DATA7 Dc-r- -- -- -- 4 slow MC70 0 -- TSR5 Dc--- -- -- 2 slow MC71 0 -- TLC0 Tc-r- Com_Ctrl_558 -- 3 slow MC72 48 PT DATA5 Dc-r- -- -- -- 4 slow MC73 49 -- MD7 INPUT TSR6 Dc--- -- -- 2 slow MC74 0 -- TCK4 Tg-r- -- -- 2 slow MC75 50 PT DATA4 Dc-r- -- -- -- 4 slow MC76 0 -- TSR7 Dc--- -- -- 2 slow MC77 51 -- MD5 INPUT TCK5 Tg-r- -- -- 2 slow MC78 0 -- CNTR_START Dc-r- -- -- 3 slow MC79 0 -- TLC1 Tc-r- -- -- 3 slow MC80 52 -- MD6 INPUT TCK3 Tg-r- -- -- 2 slow MC81 0 -- RSR2 Dc--- -- -- 2 slow MC82 0 -- RSR3 Dc--- -- -- 2 slow MC83 54 PT DATA3 Dc-r- -- -- -- 3 slow MC84 0 -- RSR1 Dc--- -- -- 2 slow MC85 55 -- MD4 INPUT RSR0 Dc--- -- -- 2 slow MC86 56 PT DATA1 Dc-r- -- -- -- 3 slow MC87 0 -- XXL_565 C---- -- -- 2 slow MC88 57 PT DATA2 Dc-r- -- -- -- 3 slow MC89 0 -- XXL_570 C---- -- -- 2 slow MC90 0 -- RSR7 Dc--- -- -- 2 slow MC91 58 -- MD3 INPUT TC0 Tc-r- -- -- 2 slow MC92 0 -- RX_FLAG Dc-r- -- -- 2 slow MC93 60 -- -- -- -- 0 slow MC94 61 -- -- -- -- 0 slow MC95 0 -- TLC3 Tc-r- -- -- 3 slow MC96 62 -- TCK INPUT TLC2 Tc-r- Com_Ctrl_558 -- 4 slow MC97 63 -- RSR5 Dc--- -- -- 2 slow MC98 0 -- RS8 Dc--- -- -- 3 slow MC99 64 -- RSR4 Dc--- -- -- 2 slow MC100 0 -- RS6 Dc--- -- -- 3 slow MC101 65 PT DATA0 Dc-r- -- -- -- 3 slow MC102 0 -- RS9 Dc--- XXL_579 -- 4 slow MC103 0 -- RS5 Dc--- -- -- 3 slow MC104 67 -- RC1 Tc-r- -- -- 3 slow MC105 68 -- RC2 Tc-r- -- -- 3 slow MC106 0 -- RS4 Dc--- -- -- 3 slow MC107 69 -- RS10 Dc--- -- -- 3 slow MC108 0 -- RS3 Dc--- -- -- 3 slow MC109 70 -- RS7 Dc--- -- -- 3 slow MC110 0 -- RS1 Dc--- XXL_569 -- 4 slow MC111 0 -- RS2 Dc--- Com_Ctrl_561 -- 4 slow MC112 71 -- TDO INPUT RS0 Dc--- NA -- 5 slow MC113 0 -- -- -- -- 0 slow MC114 0 -- -- -- -- 0 slow MC115 73 -- -- -- -- 0 slow MC116 0 -- -- -- -- 0 slow MC117 74 -- -- -- -- 0 slow MC118 75 on LED1 Dc-rp -- -- -- 3 slow MC119 0 -- -- -- -- 0 slow MC120 76 -- -- -- -- 0 slow MC121 0 -- -- -- -- 0 slow MC122 0 -- -- -- -- 0 slow MC123 77 on LED2 Dc-rp -- -- -- 3 slow MC124 0 -- -- -- -- 0 slow MC125 79 on LED0 Dc--p -- -- -- 3 slow MC126 80 -- -- -- -> BR_CLR 5 slow MC127 0 -- BR_CLR Dc-r- NA -- 4 slow MC128 81 -- CLK INPUT RSR6 Dc--- -- -- 2 slow MC0 2 -- -- -- -- 0 slow MC0 1 -- -- -- -- 0 slow MC0 84 -- -- -- -- 0 slow MC0 83 -- -- -- -- 0 slow Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades A: LC1 - LC16 15/16(93%) 4/16(25%) 3/16(18%) 55/80(68%) (26) 1 B: LC17 - LC32 16/16(100%) 7/16(43%) 1/16(6%) 41/80(51%) (29) 0 C: LC33 - LC48 16/16(100%) 8/16(50%) 1/16(6%) 39/80(48%) (26) 0 D: LC49 - LC64 16/16(100%) 7/16(43%) 1/16(6%) 40/80(50%) (36) 0 E: LC65 - LC80 16/16(100%) 7/16(43%) 1/16(6%) 42/80(52%) (37) 0 F: LC81 - LC96 14/16(87%) 6/16(37%) 1/16(6%) 34/80(42%) (37) 0 G: LC97 - LC112 16/16(100%) 2/16(12%) 3/16(18%) 51/80(63%) (22) 0 H: LC113- LC128 5/16(31%) 4/16(25%) 0/16(0%) 20/80(25%) (36) 1 Total dedicated input used: 0/4 (0%) Total I/O pins used 45/64 (70%) Total Logic cells used 116/128 (90%) Total Flip-Flop used 99/128 (77%) Total Foldback logic used 11/128 (8%) Total Nodes+FB/MCells 125/128 (97%) Total cascade used 2 Total input pins 24 Total output pins 21 Total Pts 322 Creating pla file C:\USERS\MALCOLM\ONEDRIVE\OMNIBUS-SERIAL-BOARD\CUPL-FILES\MAIN.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms... ---------------- End fitter, Design FITS $Device PLCC84 fits FIT1508 completed in 0.00 seconds