{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1551332672477 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1551332672585 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 27 21:44:31 2019 " "Processing started: Wed Feb 27 21:44:31 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1551332672585 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1551332672585 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off warv -c war " "Command: quartus_map --read_settings_files=on --write_settings_files=off warv -c war" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1551332672585 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1551332678131 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "war.v " "Can't analyze file -- file war.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1551332678822 ""}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "warv.v(226) " "Verilog HDL syntax warning at warv.v(226): extra block comment delimiter characters /* within block comment" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 226 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "Quartus II" 0 -1 1551332678883 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "warv.v 1 1 " "Found 1 design units, including 1 entities, in source file warv.v" { { "Info" "ISGN_ENTITY_NAME" "1 warv " "Found entity 1: warv" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1551332678897 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1551332678897 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "warv " "Elaborating entity \"warv\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1551332679036 ""}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y03 warv.v(424) " "Verilog HDL Always Construct warning at warv.v(424): inferring latch(es) for variable \"y03\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 424 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679118 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y02 warv.v(424) " "Verilog HDL Always Construct warning at warv.v(424): inferring latch(es) for variable \"y02\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 424 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679118 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x03 warv.v(431) " "Verilog HDL Always Construct warning at warv.v(431): inferring latch(es) for variable \"x03\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 431 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679118 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x02 warv.v(431) " "Verilog HDL Always Construct warning at warv.v(431): inferring latch(es) for variable \"x02\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 431 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679119 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y07 warv.v(438) " "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"y07\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679119 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y06 warv.v(438) " "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"y06\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679119 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y05 warv.v(438) " "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"y05\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679119 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y04 warv.v(438) " "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"y04\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679119 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x07 warv.v(450) " "Verilog HDL Always Construct warning at warv.v(450): inferring latch(es) for variable \"x07\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679120 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x06 warv.v(450) " "Verilog HDL Always Construct warning at warv.v(450): inferring latch(es) for variable \"x06\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679120 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x05 warv.v(450) " "Verilog HDL Always Construct warning at warv.v(450): inferring latch(es) for variable \"x05\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679134 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x04 warv.v(450) " "Verilog HDL Always Construct warning at warv.v(450): inferring latch(es) for variable \"x04\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679134 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y11 warv.v(461) " "Verilog HDL Always Construct warning at warv.v(461): inferring latch(es) for variable \"y11\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679134 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y10 warv.v(461) " "Verilog HDL Always Construct warning at warv.v(461): inferring latch(es) for variable \"y10\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679134 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y09 warv.v(461) " "Verilog HDL Always Construct warning at warv.v(461): inferring latch(es) for variable \"y09\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679135 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "y08 warv.v(461) " "Verilog HDL Always Construct warning at warv.v(461): inferring latch(es) for variable \"y08\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679135 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x11 warv.v(472) " "Verilog HDL Always Construct warning at warv.v(472): inferring latch(es) for variable \"x11\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679135 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x10 warv.v(472) " "Verilog HDL Always Construct warning at warv.v(472): inferring latch(es) for variable \"x10\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679135 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x09 warv.v(472) " "Verilog HDL Always Construct warning at warv.v(472): inferring latch(es) for variable \"x09\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "x08 warv.v(472) " "Verilog HDL Always Construct warning at warv.v(472): inferring latch(es) for variable \"x08\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_enable warv.v(512) " "Verilog HDL Always Construct warning at warv.v(512): inferring latch(es) for variable \"int_enable\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 512 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "device_flag warv.v(517) " "Verilog HDL Always Construct warning at warv.v(517): inferring latch(es) for variable \"device_flag\", which holds its previous value in one or more paths through the always construct" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 517 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "device_flag warv.v(517) " "Inferred latch for \"device_flag\" at warv.v(517)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 517 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_enable warv.v(512) " "Inferred latch for \"int_enable\" at warv.v(512)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 512 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679136 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x08 warv.v(472) " "Inferred latch for \"x08\" at warv.v(472)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x09 warv.v(472) " "Inferred latch for \"x09\" at warv.v(472)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x10 warv.v(472) " "Inferred latch for \"x10\" at warv.v(472)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x11 warv.v(472) " "Inferred latch for \"x11\" at warv.v(472)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 472 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y08 warv.v(461) " "Inferred latch for \"y08\" at warv.v(461)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y09 warv.v(461) " "Inferred latch for \"y09\" at warv.v(461)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y10 warv.v(461) " "Inferred latch for \"y10\" at warv.v(461)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679137 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y11 warv.v(461) " "Inferred latch for \"y11\" at warv.v(461)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 461 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x04 warv.v(450) " "Inferred latch for \"x04\" at warv.v(450)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x05 warv.v(450) " "Inferred latch for \"x05\" at warv.v(450)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x06 warv.v(450) " "Inferred latch for \"x06\" at warv.v(450)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x07 warv.v(450) " "Inferred latch for \"x07\" at warv.v(450)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 450 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y04 warv.v(438) " "Inferred latch for \"y04\" at warv.v(438)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y05 warv.v(438) " "Inferred latch for \"y05\" at warv.v(438)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679138 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y06 warv.v(438) " "Inferred latch for \"y06\" at warv.v(438)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679139 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y07 warv.v(438) " "Inferred latch for \"y07\" at warv.v(438)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 438 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679139 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x02 warv.v(431) " "Inferred latch for \"x02\" at warv.v(431)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 431 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679139 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x03 warv.v(431) " "Inferred latch for \"x03\" at warv.v(431)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 431 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679139 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y02 warv.v(424) " "Inferred latch for \"y02\" at warv.v(424)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 424 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679140 "|warv"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y03 warv.v(424) " "Inferred latch for \"y03\" at warv.v(424)" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 424 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1551332679140 "|warv"}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "device_flag " "LATCH primitive \"device_flag\" is permanently disabled" {  } { { "warv.v" "" { Text "C:/Users/Vince/Documents/warv/warv.v" 200 -1 0 } }  } 0 14025 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "Quartus II" 0 -1 1551332680534 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "113 " "Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1551332681737 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1551332681737 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "12 " "Implemented 12 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1551332681737 ""} { "Info" "ICUT_CUT_TM_MCELLS" "40 " "Implemented 40 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1551332681737 ""} { "Info" "ICUT_CUT_TM_SEXPS" "9 " "Implemented 9 shareable expanders" {  } {  } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1551332681737 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1551332681737 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "409 " "Peak virtual memory: 409 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1551332683352 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 27 21:44:43 2019 " "Processing ended: Wed Feb 27 21:44:43 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1551332683352 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1551332683352 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1551332683352 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1551332683352 ""}