# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 18:22:45 February 17, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # war_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY MAX7000S set_global_assignment -name DEVICE "EPM7128SLC84-15" set_global_assignment -name TOP_LEVEL_ENTITY warv set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:22:45 FEBRUARY 17, 2019" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL set_location_assignment PIN_25 -to initialize set_location_assignment PIN_50 -to md3_low set_location_assignment PIN_44 -to md4_low set_location_assignment PIN_41 -to md5_low set_location_assignment PIN_40 -to md6_low set_location_assignment PIN_39 -to md7_low set_location_assignment PIN_22 -to md8_low set_location_assignment PIN_21 -to md9_low set_location_assignment PIN_20 -to md10_low set_location_assignment PIN_18 -to md11_low set_location_assignment PIN_54 -to n_t_35x set_location_assignment PIN_33 -to pause_low set_location_assignment PIN_2 -to d00_l set_location_assignment PIN_4 -to d01_l set_location_assignment PIN_5 -to d02_l set_location_assignment PIN_6 -to d03_l set_location_assignment PIN_8 -to d08_l set_location_assignment PIN_9 -to d09_l set_location_assignment PIN_10 -to d10_l set_location_assignment PIN_11 -to d11_l set_location_assignment PIN_52 -to set_done set_location_assignment PIN_29 -to tp3 set_location_assignment PIN_55 -to b_dixy_low set_location_assignment PIN_51 -to btp3 set_location_assignment PIN_31 -to c0_low set_location_assignment PIN_30 -to c1_low set_location_assignment PIN_57 -to chan_low set_location_assignment PIN_56 -to col_red_low set_location_assignment PIN_49 -to data00_low set_location_assignment PIN_48 -to data01_low set_location_assignment PIN_46 -to data02_low set_location_assignment PIN_45 -to data03_low set_location_assignment PIN_37 -to data04_low set_location_assignment PIN_36 -to data05_low set_location_assignment PIN_35 -to data06_low set_location_assignment PIN_34 -to data07_low set_location_assignment PIN_12 -to data11_low set_location_assignment PIN_15 -to data10_low set_location_assignment PIN_16 -to data09_low set_location_assignment PIN_17 -to data08_low set_location_assignment PIN_63 -to dly_done_low set_location_assignment PIN_58 -to erase_low set_location_assignment PIN_28 -to internal_io_low set_location_assignment PIN_27 -to interrupt_low set_location_assignment PIN_77 -to load_x set_location_assignment PIN_79 -to load_y set_location_assignment PIN_61 -to n_t_27x set_location_assignment PIN_24 -to skip_low set_location_assignment PIN_60 -to write_thru_low set_location_assignment PIN_64 -to di02_l set_location_assignment PIN_65 -to di03 set_location_assignment PIN_67 -to di04 set_location_assignment PIN_68 -to di05 set_location_assignment PIN_69 -to di06 set_location_assignment PIN_70 -to di07 set_location_assignment PIN_73 -to di08 set_location_assignment PIN_74 -to di09 set_location_assignment PIN_75 -to di10 set_location_assignment PIN_76 -to di11 set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84 set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name VERILOG_FILE warv.v set_location_assignment PIN_1 -to grn_delay set_location_assignment PIN_83 -to red_delay set_location_assignment PIN_80 -to non_store_low set_location_assignment PIN_81 -to ld_del_low set_location_assignment PIN_84 -to del_1_low