{ "" "" "" "Verilog HDL syntax warning at war.v(226): extra block comment delimiter characters /* within block comment" {  } {  } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(424): inferring latch(es) for variable \"y03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(424): inferring latch(es) for variable \"y02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(431): inferring latch(es) for variable \"x03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(431): inferring latch(es) for variable \"x02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(438): inferring latch(es) for variable \"y07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(438): inferring latch(es) for variable \"y06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(438): inferring latch(es) for variable \"y05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(438): inferring latch(es) for variable \"y04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(450): inferring latch(es) for variable \"x07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(450): inferring latch(es) for variable \"x06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(450): inferring latch(es) for variable \"x05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(450): inferring latch(es) for variable \"x04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(461): inferring latch(es) for variable \"y11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(461): inferring latch(es) for variable \"y10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(461): inferring latch(es) for variable \"y09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(461): inferring latch(es) for variable \"y08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(472): inferring latch(es) for variable \"x11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(472): inferring latch(es) for variable \"x10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(472): inferring latch(es) for variable \"x09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(472): inferring latch(es) for variable \"x08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(512): inferring latch(es) for variable \"int_enable\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at war.v(517): inferring latch(es) for variable \"device_flag\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Node \"TCK\" is assigned to location or region, but does not exist in design" {  } {  } 0 15706 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Node \"TDI\" is assigned to location or region, but does not exist in design" {  } {  } 0 15706 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Node \"TDO\" is assigned to location or region, but does not exist in design" {  } {  } 0 15706 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Node \"TMS\" is assigned to location or region, but does not exist in design" {  } {  } 0 15706 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(431): inferring latch(es) for variable \"y03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(431): inferring latch(es) for variable \"y02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"x03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(438): inferring latch(es) for variable \"x02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(445): inferring latch(es) for variable \"y07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(445): inferring latch(es) for variable \"y06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(445): inferring latch(es) for variable \"y05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(445): inferring latch(es) for variable \"y04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(457): inferring latch(es) for variable \"x07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(457): inferring latch(es) for variable \"x06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(457): inferring latch(es) for variable \"x05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(457): inferring latch(es) for variable \"x04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(468): inferring latch(es) for variable \"y11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(468): inferring latch(es) for variable \"y10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(468): inferring latch(es) for variable \"y09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(468): inferring latch(es) for variable \"y08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(479): inferring latch(es) for variable \"x11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(479): inferring latch(es) for variable \"x10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(479): inferring latch(es) for variable \"x09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(479): inferring latch(es) for variable \"x08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(519): inferring latch(es) for variable \"int_enable\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(524): inferring latch(es) for variable \"device_flag\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(433): inferring latch(es) for variable \"y03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(433): inferring latch(es) for variable \"y02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(481): inferring latch(es) for variable \"x10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(481): inferring latch(es) for variable \"x09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(481): inferring latch(es) for variable \"x08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(521): inferring latch(es) for variable \"int_enable\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(526): inferring latch(es) for variable \"device_flag\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(459): inferring latch(es) for variable \"x05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(459): inferring latch(es) for variable \"x04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(470): inferring latch(es) for variable \"y11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(470): inferring latch(es) for variable \"y10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(470): inferring latch(es) for variable \"y09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(470): inferring latch(es) for variable \"y08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(481): inferring latch(es) for variable \"x11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(447): inferring latch(es) for variable \"y07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(447): inferring latch(es) for variable \"y06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(447): inferring latch(es) for variable \"y05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(447): inferring latch(es) for variable \"y04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(459): inferring latch(es) for variable \"x07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(459): inferring latch(es) for variable \"x06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(440): inferring latch(es) for variable \"x03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(440): inferring latch(es) for variable \"x02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"device_flag\" at warv.v(526)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"int_enable\" at warv.v(521)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x08\" at warv.v(481)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x09\" at warv.v(481)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x10\" at warv.v(481)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x11\" at warv.v(481)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y08\" at warv.v(470)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y09\" at warv.v(470)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y10\" at warv.v(470)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y11\" at warv.v(470)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x04\" at warv.v(459)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x05\" at warv.v(459)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x06\" at warv.v(459)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x07\" at warv.v(459)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y04\" at warv.v(447)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y05\" at warv.v(447)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y06\" at warv.v(447)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y07\" at warv.v(447)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x02\" at warv.v(440)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"x03\" at warv.v(440)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y02\" at warv.v(433)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred latch for \"y03\" at warv.v(433)" {  } {  } 0 10041 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL syntax warning at warv.v(235): extra block comment delimiter characters /* within block comment" {  } {  } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(451): inferring latch(es) for variable \"y03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(451): inferring latch(es) for variable \"y02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(458): inferring latch(es) for variable \"x03\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(458): inferring latch(es) for variable \"x02\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable \"y07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable \"y06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable \"y05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable \"y04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(477): inferring latch(es) for variable \"x07\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(477): inferring latch(es) for variable \"x06\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(477): inferring latch(es) for variable \"x05\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(477): inferring latch(es) for variable \"x04\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(488): inferring latch(es) for variable \"y11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(488): inferring latch(es) for variable \"y10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(488): inferring latch(es) for variable \"y09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(488): inferring latch(es) for variable \"y08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(499): inferring latch(es) for variable \"x11\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(499): inferring latch(es) for variable \"x10\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(499): inferring latch(es) for variable \"x09\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(499): inferring latch(es) for variable \"x08\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(539): inferring latch(es) for variable \"int_enable\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at warv.v(544): inferring latch(es) for variable \"device_flag\", which holds its previous value in one or more paths through the always construct" {  } {  } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" {  } {  } 0 20028 "" 0 0 "Quartus II" 0 -1 0 ""}