Pinlist Exported from pdp8l.sch at 3/18/2020 3:07:39 PM EAGLE Version 6.6.0 Copyright (c) 1988-2014 CadSoft Part Pad Pin Dir Net A01 A1 P$2 io !KEY_PROTECT A2 P$2 io VCC B1 P$2 io B36S1 B2 P$2 io A01B2 C1 P$2 io B36P1 C2 P$2 io GND D1 P$2 io SR04 D2 P$2 io SR03 E1 P$2 io !LINK E2 P$2 io SR02 F1 P$2 io !EMA F2 P$2 io SR01 H1 P$2 io !MB01 H2 P$2 io SR00 J1 P$2 io !MA01 J2 P$2 io !AC00 K1 P$2 io !AC03 K2 P$2 io !MB00 L1 P$2 io !AC02 L2 P$2 io !AC01 M1 P$2 io *** unused *** M2 P$2 io !MA00 N1 P$2 io *** unused *** N2 P$2 io !MB02 P1 P$2 io *** unused *** P2 P$2 io !MA02 R1 P$2 io *** unused *** R2 P$2 io !MB03 S1 P$2 io *** unused *** S2 P$2 io !MA03 T1 P$2 io GND T2 P$2 io !MB04 U1 P$2 io *** unused *** U2 P$2 io !MA04 V1 P$2 io A01_10V V2 P$2 io *** unused *** A08 A1 IN1 in C12U1 A2 VCC pwr VCC B1 IN2 in C12H2 C1 IN3 in B13F2 C2 GND pwr GND D1 IN4 in C12U1 D2 IN1 in C12J1 E1 OUT oc SR_ENABLE E2 IN2 in !MA_ENABLE(5-11) F1 IN1 in !!AC_ENABLE F2 IN3 in !MA_ENABLE(5-11) H1 IN2 in !!AC_ENABLE H2 IN4 in !MA_ENABLE(5-11) J1 IN3 in !!AC_ENABLE J2 OUT oc MA_ENABLE(0-4) K1 IN4 in !!AC_ENABLE K2 IN1 in !ADD L1 OUT oc !AC_ENABLE L2 IN2 in A10R1 M1 IN1 in !IOP4 M2 IN3 in A10R1 N1 IN2 in !IOP2 N2 IN4 in !PROTECT P1 IN3 in !IOP1 P2 OUT oc MEM_ENABLE(0-4) R1 IN4 in +3V(18) R2 IN1 in C12N1 S1 OUT oc IO_ENABLE S2 IN2 in !INT_SKIP_EN T1 GND pwr GND T2 IN3 in !PC_ENABLE U1 P$1 pas +3V(18) U2 IN4 in !IO_PC_ENABLE V1 P$1 pas *** unused *** V2 OUT oc PC_ENABLE A09 A1 IN1 in A11N1 A2 VCC pwr VCC B1 IN2 in A11N1 C1 IN3 in OP1 C2 GND pwr GND D1 IN4 in OP1 D2 IN1 in !MA_ENABLE(5-11) E1 OUT oc NO_SHIFT E2 IN2 in !MA_ENABLE(5-11) F1 IN1 in !AND_ENABLE F2 IN3 in !MA_ENABLE(5-11) H1 IN2 in D09T2 H2 IN4 in !MA_ENABLE(5-11) J1 IN3 in D09T2 J2 OUT oc MA_ENABLE(5-11) K1 IN4 in !ADD K2 IN1 in !JMP_DIRECT L1 OUT oc AC_ENABLE L2 IN2 in !JMP_DIRECT M1 IN1 in !DATA_ENABLE M2 IN3 in !MEM_ENABLE(0-4) N1 IN2 in !DATA_ENABLE N2 IN4 in C13L1 P1 IN3 in !DATA_ENABLE P2 OUT oc MEM_ENABLE(5-11) R1 IN4 in !DATA_ENABLE R2 IN1 in !DATA_ADD_EN S1 OUT oc DATA_ENABLE S2 IN2 in !DATA_ADD_EN T1 GND pwr GND T2 IN3 in !DATA_ADD_EN U1 P$1 pas +3V(6) U2 IN4 in !DATA_ADD_EN V1 P$1 pas +3V(9) V2 OUT oc DATA_ADD_EN A10 A1 IN1A in TS3 A2 VCC pwr VCC B1 IN1B in +3V(6) C1 IN1C in DEFER C2 GND pwr GND D1 IN1D in JMP D2 IN1A in B_EXECUTE E1 IN2A in TS2 E2 IN1B in +3V(6) F1 IN2B in !MEM_ALT1 F2 IN1C in JMS H1 IN3A in +3V(6) H2 IN1D in +3V(6) J1 IN3B in GND J2 IN2A in DCA K1 IN4A in TS4 K2 IN2B in B_EXECUTE L1 IN4B in B_CA L2 IN3A in B_BK M1 IN5A in TS4 M2 IN3B in DATA_IN N1 IN5B in DEFER N2 IN4A in MFTS3 P1 IN5C in !JMP P2 IN4B in KEY_DP R1 OUT out A10R1 R2 IN4C in KEY_DP S1 IN1A in LINK S2 IN4D in KEY_DP T1 GND pwr GND T2 OUT out !MEM_ALT1 U1 IN1B in L_ENABLE U2 IN2B in !L_ENABLE V1 IN2A in !LINK V2 OUT out A10V2 A11 A1 IN1 in MB09 A2 VCC pwr VCC B1 IN2 in OP1 C1 IN3 in MB10 C2 GND pwr GND D1 OUT out !DOUBLE_LEFT_ROTATE D2 IN1 in MB08 E1 IN1 in MB08 E2 IN2 in OP1 F1 IN2 in OP1 F2 IN3 in MB10 H1 IN3 in !MB10 H2 OUT out !DOUBLE_RIGHT_ROTATE J1 OUT out !RIGHT_SHIFT J2 IN1 in MB09 K1 IN1 in !MB08 K2 IN2 in OP1 L1 IN2 in OP1 L2 IN3 in !MB10 M1 IN3 in !MB09 M2 OUT out !LEFT_SHIFT N1 OUT out A11N1 N2 IN1 in A12R1 P1 IN1 in AND P2 IN2 in !MEM_ALT2 R1 IN2 in TS3 R2 IN3 in !WORD_COUNT S1 IN3 in B_EXECUTE S2 OUT out A11S2 T1 GND pwr GND T2 IN1 in !OP_STROBE U1 OUT out !AND_ENABLE U2 IN2 in C14F2 V1 OUT out A11V1 V2 IN3 in C12V1 A12 A1 IN1A in B12M1 A2 VCC pwr VCC B1 IN1B in MEM_ENABLE(0-4) C1 IN1C in DEFER C2 GND pwr GND D1 IN1D in MA08 D2 IN1A in TS2 E1 IN2A in TS1 E2 IN1B in B_EXECUTE F1 IN2B in FETCH F2 IN1C in ISZ H1 IN3A in OP1 H2 IN1D in +3V(9) J1 IN3B in MB11 J2 IN2A in MFTS2 K1 IN4A in A14V1 K2 IN2B in KEY_EX+DP L1 IN4B in SKIP L2 IN3A in CA_INCREMENT M1 IN5A in TS3 M2 IN3B in B_CA N1 IN5B in B_EXECUTE N2 IN4A in +3V(9) P1 IN5C in JMS P2 IN4B in TS2 R1 OUT out A12R1 R2 IN4C in MEMORY_INCREMENT S1 IN1A in A13V2 S2 IN4D in B_BK T1 GND pwr GND T2 OUT out !MEM_ALT2 U1 IN1B in OP1 U2 IN2B in KEY_ST V1 IN2A in MFTS2 V2 OUT out L_ENABLE A13 A1 IN1A in TP3 A2 VCC pwr VCC B1 IN1B in JMS C1 IN1C in B_EXECUTE C2 GND pwr GND D1 IN1D in !ILLEGAL_REF D2 IN1A in TS2 E1 IN2A in TP1 E2 IN1B in B_EXECUTE F1 IN2B in B_FETCH F2 IN1C in CARRYOUT0 H1 IN3A in TP3 H2 IN1D in ISZ J1 IN3B in JMP_DIRECT J2 IN2A in IO_ENABLE K1 IN4A in MFTP2 K2 IN2B in IO_SKIP L1 IN4B in KEY_LA+EX+DP L2 IN3A in B12T2 M1 IN5A in TP3 M2 IN3B in !MB08 N1 IN5B in DEFER N2 IN4A in C14K2 P1 IN5C in JMP P2 IN4B in OP2 R1 OUT out A13R1 R2 IN4C in MB08 S1 IN1A in !MB05 S2 IN4D in C14K2 T1 GND pwr GND T2 OUT out A13T2 U1 IN1B in !MB07 U2 IN2B in MB07 V1 IN2A in MB05 V2 OUT out A13V2 A14 A1 IN1 in C14N1 A2 VCC pwr VCC B1 IN2 in A14J1 C1 IN3 in C14N2 C2 GND pwr GND D1 OUT out A14D1 D2 IN1 in !TTI_FLAG E1 IN1 in B12S1 E2 IN2 in !TTO_FLAG F1 IN2 in MB06 F2 IN3 in !MP_INT H1 IN3 in B12U1 H2 OUT out TT_INT J1 OUT out A14J1 J2 IN1 in A14U1 K1 IN1 in A14M2 K2 IN2 in MP_INT L1 IN2 in A14M2 L2 IN3 in MP_INT M1 IN3 in !CLR_PARITY_ERROR M2 OUT out A14M2 N1 OUT out MP_INT N2 IN1 in !TTI_SKIP P1 IN1 in MEM_PARITY_EVEN P2 IN2 in !TTO_SKIP R1 IN2 in MEM_PARITY_EVEN R2 IN3 in !MP_SKIP S1 IN3 in TP3 S2 OUT out TT_SKIP T1 GND pwr GND T2 IN1 in !INT_SKIP_EN U1 OUT out A14U1 U2 IN2 in !IO_PC_ENABLE V1 OUT out A14V1 V2 IN3 in !PC_ENABLE A15 A1 1B in !MEM00 A2 VCC pwr VCC B1 2B in !MEM01 C1 4B in !MEM02 C2 GND pwr GND D1 8B in !MEM03 E1 1A in MEM00 F1 2A in MEM01 H1 4A in MEM02 J1 8A in MEM03 K1 ODD out A15K1 K2 1B in !MEM08 L1 EVEN out A15L1 L2 2B in !MEM09 M2 4B in !MEM10 N2 8B in !MEM11 P2 1A in MEM08 R2 2A in MEM09 S2 4A in MEM10 T1 GND pwr GND T2 8A in MEM11 U2 ODD out A15U2 V2 EVEN out A15V2 A16 A1 1B in A15L1 A2 VCC pwr VCC B1 2B in A16V2 C1 4B in A15V2 C2 GND pwr GND D1 8B in !MEM_P E1 1A in A15K1 F1 2A in A16U2 H1 4A in A15U2 J1 8A in MEM_P K1 ODD out *** unconnected *** K2 1B in !MEM04 L1 EVEN out MEM_PARITY_EVEN L2 2B in !MEM05 M2 4B in !MEM06 N2 8B in !MEM07 P2 1A in MEM04 R2 2A in MEM05 S2 4A in MEM06 T1 GND pwr GND T2 8A in MEM07 U2 ODD out A16U2 V2 EVEN out A16V2 A17 A1 A1 oc MEM_P A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in A21S2 E1 E1 out *** unconnected *** E2 E2 in A21T2 K2 K2 out *** unconnected *** L1 L1 in GND M1 M1 in GND R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc *** unconnected *** A18 A1 A1 oc MEM00 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in A21C2 E1 E1 out *** unconnected *** E2 E2 in A21D2 K2 K2 out *** unconnected *** L1 L1 in A21E2 M1 M1 in A21F2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM01 A19 A1 A1 oc MEM02 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in A21H2 E1 E1 out *** unconnected *** E2 E2 in A21J2 K2 K2 out *** unconnected *** L1 L1 in A21K2 M1 M1 in A21L2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM03 A20 A1 A1 oc MEM04 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in A21M2 E1 E1 out *** unconnected *** E2 E2 in A21N2 K2 K2 out *** unconnected *** L1 L1 in A21P2 M1 M1 in A21R2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM05 A21 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io A21C2 D2 P$2 io A21D2 E2 P$2 io A21E2 F2 P$2 io A21F2 H2 P$2 io A21H2 J2 P$2 io A21J2 K2 P$2 io A21K2 L2 P$2 io A21L2 M2 P$2 io A21M2 N2 P$2 io A21N2 P2 P$2 io A21P2 R2 P$2 io A21R2 S2 P$2 io A21S2 T2 P$2 io A21T2 U2 P$2 io *** unused *** V2 P$2 io *** unused *** A22 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io A23J2 D2 P$2 io A23K2 E2 P$2 io A23H1 F2 P$2 io A23J1 H2 P$2 io A23S2 J2 P$2 io A23T2 K2 P$2 io A23P1 L2 P$2 io A23R1 M2 P$2 io B23J2 N2 P$2 io B23K2 P2 P$2 io B23H1 R2 P$2 io B23J1 S2 P$2 io A24J2 T2 P$2 io A24K2 U2 P$2 io *** unused *** V2 P$2 io *** unused *** A23 A1 A1 in B_INHIBIT A2 VCC pwr VCC C2 GND pwr GND D1 D1 in !MB01 D2 D2 in !MB00 E1 E1 pas A23E1 E2 E2 in B_MEM_ENABLE F1 H in A25R2 F2 F2 pas A23F2 H1 J pas A23H1 H2 H in A25P2 J1 K pas A23J1 J2 J pas A23J2 K1 K1 pas MEM_SUPPLY+ K2 K pas A23K2 L1 L1 in !MB03 L2 L2 pas MEM_SUPPLY+ M1 M1 pas A23M1 M2 M2 in !MB02 N1 H in A25T2 N2 N2 in B_MEM_ENABLE P1 J pas A23P1 P2 P2 pas A23P2 R1 K pas A23R1 R2 H in A25S2 S1 S1 pas MEM_SUPPLY+ S2 J pas A23S2 T1 GND pwr GND T2 K pas A23T2 U2 U2 pas MEM_SUPPLY+ V2 V2 in MEM_SUPPLY- A24 A1 A1 in B_INHIBIT A2 VCC pwr VCC C2 GND pwr GND D1 D1 in GND D2 D2 in MB_PARITY_ODD E1 E1 pas *** unconnected *** E2 E2 in B_MEM_ENABLE F1 H in *** unused *** F2 F2 pas A24F2 H1 J pas *** unused *** H2 H in A26P2 J1 K pas *** unused *** J2 J pas A24J2 K1 K1 pas *** unconnected *** K2 K pas A24K2 L1 L1 in GND L2 L2 pas MEM_SUPPLY+ M1 M1 pas *** unconnected *** M2 M2 in GND N1 H in *** unused *** N2 N2 in GND P1 J pas *** unused *** P2 P2 pas *** unconnected *** R1 K pas *** unused *** R2 H in *** unused *** S1 S1 pas *** unconnected *** S2 J pas *** unused *** T1 GND pwr GND T2 K pas *** unused *** U2 U2 pas *** unconnected *** V2 V2 in MEM_SUPPLY- A25 B2 P$1 pas MEM_RET C2 P$2 pas *** unused *** D2 P$2 pas Y_R/W_RETURN E2 P$2 pas GND F2 P$1 pas A25F2 H2 P$1 pas MEM_SUPPLY- J2 P$3 pas MEM_SUPPLY+ K2 P$1 pas A23M1 L2 P$1 pas A23P2 M2 P$1 pas A23E1 N2 P$1 pas A23F2 P2 P$2 pas A25P2 R2 P$2 pas A25R2 S2 P$2 pas A25S2 T2 P$2 pas A25T2 U2 P$2 pas MEM_SUPPLY+ V2 P$1 pas *** unused *** A26 B2 P$1 pas MEM_RET C2 P$2 pas *** unused *** D2 P$2 pas X_R/W_SOURCE E2 P$2 pas MEM_SUPPLY+ F2 P$1 pas A26F2 H2 P$1 pas MEM_SUPPLY- J2 P$3 pas MEM_SUPPLY+ K2 P$1 pas *** unused *** L2 P$1 pas *** unused *** M2 P$1 pas MEM_SUPPLY- N2 P$1 pas A24F2 P2 P$2 pas A26P2 R2 P$2 pas NEG_CLAMP S2 P$2 pas *** unused *** T2 P$2 pas *** unused *** U2 P$2 pas MEM_SUPPLY+ V2 P$1 pas *** unused *** A27 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io *** unused *** D2 P$2 io *** unused *** E2 P$2 io *** unused *** F2 P$2 io !SHUT_DOWN H2 P$2 io STOP_OK J2 P$2 io !POWER_OK K2 P$2 io *** unused *** L2 P$2 io *** unused *** M2 P$2 io *** unused *** N2 P$2 io *** unused *** P2 P$2 io *** unused *** R2 P$2 io *** unused *** S2 P$2 io !POWER_CLEAR T2 P$2 io B36V2 U2 P$2 io *** unused *** V2 P$2 io *** unused *** A28 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io A01B2 C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io *** unused *** D2 P$2 io GND E1 P$2 io B36T2 E2 P$2 io GND F1 P$2 io *** unused *** F2 P$2 io +5V(1) H1 P$2 io *** unused *** H2 P$2 io +5V(2) J1 P$2 io *** unused *** J2 P$2 io +5V(3) K1 P$2 io *** unused *** K2 P$2 io +5V(4) L1 P$2 io *** unused *** L2 P$2 io +5V(5) M1 P$2 io *** unused *** M2 P$2 io +5V(6) N1 P$2 io *** unused *** N2 P$2 io A01_10V P1 P$2 io *** unused *** P2 P$2 io B01_10V R1 P$2 io *** unused *** R2 P$2 io C01_10V S1 P$2 io *** unused *** S2 P$2 io D01_10V T1 P$2 io *** unused *** T2 P$2 io PANEL_LOCK U1 P$2 io *** unused *** U2 P$2 io B36V2 V1 P$2 io *** unused *** V2 P$2 io SLICE A32 A1 IN in !IB04 A2 VCC pwr VCC B1 IN2 io !INT_IO_BUS4 C1 IN3 in !TT0 C2 GND pwr GND D1 IN4 in !INT_IO_BUS4 D2 IN in !IB05 E1 OUT out INPUT_BUS04 E2 IN2 io !INT_IO_BUS5 F1 IN in !IB06 F2 IN3 in !TT1 H1 IN2 io !INT_IO_BUS6 H2 IN4 in !INT_IO_BUS5 J1 IN3 in !TT2 J2 OUT out INPUT_BUS05 K1 IN4 in !INT_IO_BUS6 K2 IN in !IB07 L1 OUT out INPUT_BUS06 L2 IN2 io !INT_IO_BUS7 M1 IN in !IB08 M2 IN3 in !TT3 N1 IN2 io !INT_IO_BUS8 N2 IN4 in !INT_IO_BUS7 P1 IN3 in !TT4 P2 OUT out INPUT_BUS07 R1 IN4 in !INT_IO_BUS8 R2 IN in !IB09 S1 OUT out INPUT_BUS08 S2 IN2 io !INT_IO_BUS9 T1 GND pwr GND T2 IN3 in !TT5 U2 IN4 in !INT_IO_BUS9 V2 OUT out INPUT_BUS09 A33 A1 IN in !IB10 A2 VCC pwr VCC B1 IN2 io !INT_IO_BUS10 C1 IN3 in !TT6 C2 GND pwr GND D1 IN4 in !INT_IO_BUS10 D2 IN in !IB11 E1 OUT out INPUT_BUS10 E2 IN2 io !INT_IO_BUS11 F1 IN in !BSKIP F2 IN3 in !TT7 H1 IN2 io !RDR_SKP H2 IN4 in !INT_IO_BUS11 J1 IN3 in !TT_SKIP J2 OUT out INPUT_BUS11 K1 IN4 in !PWR_SKP K2 IN in !BIRQ L1 OUT out IO_SKIP L2 IN2 io !RDR_INT M1 IN in !BAC_CLEAR M2 IN3 in !TT_INT N1 IN2 io !TT_AC_CLEAR N2 IN4 in !PWR_LOW P1 IN3 in !TT_AC_CLEAR P2 OUT out INT_RQST R1 IN4 in !TT_AC_CLEAR R2 IN in !BMEM_INCR S1 OUT out AC_CLEAR S2 IN2 io A33S2 T1 GND pwr GND T2 IN3 in A33S2 U2 IN4 in A33S2 V2 OUT out MEMORY_INCREMENT A34 A1 IN in !BADDR09 A2 VCC pwr VCC B1 OUT out DATA_ADD09 C1 IN in !BADDR10 C2 GND pwr GND D1 IN in !BADDR11 D2 OUT out DATA_ADD10 E1 OUT out DATA_ADD11 E2 IN in !BDATA06 F1 IN in !BDATA00 F2 OUT out DATA06 H1 OUT out DATA00 H2 IN in !BDATA07 J1 IN in !BDATA01 J2 OUT out DATA07 K1 OUT out DATA01 K2 IN in !BDATA08 L1 IN in !BDATA02 L2 OUT out DATA08 M1 OUT out DATA02 M2 IN in !BDATA09 N1 IN in !BDATA03 N2 OUT out DATA09 P1 OUT out DATA03 P2 IN in !BDATA10 R1 IN in !BDATA04 R2 OUT out DATA10 S1 OUT out DATA04 S2 IN in !BDATA11 T1 GND pwr GND T2 OUT out DATA11 U1 OUT out DATA05 U2 IN in !3CYCLE V1 IN in !BDATA05 V2 OUT out 3CYCLE A35 A1 IN in D12V2 A2 VCC pwr VCC B1 OUT out B36D1 C1 IN in B_SET C2 GND pwr GND D1 IN in IO_ENABLE D2 OUT out B36E1 E1 OUT out !IO_ENABLE E2 IN in !MA05 F1 IN in *** unused *** F2 OUT out MMA05 H1 OUT out *** unused *** H2 IN in !MA06 J1 IN in !MA00 J2 OUT out MMA06 K1 OUT out MMA00 K2 IN in !MA07 L1 IN in !MA01 L2 OUT out MMA07 M1 OUT out MMA01 M2 IN in !MA08 N1 IN in !MA02 N2 OUT out MMA08 P1 OUT out MMA02 P2 IN in !MA09 R1 IN in !MA03 R2 OUT out MMA09 S1 OUT out MMA03 S2 IN in !MA10 T1 GND pwr GND T2 OUT out MMA10 U1 OUT out MMA04 U2 IN in !MA11 V1 IN in !MA04 V2 OUT out MMA11 A36 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io *** unused *** D2 P$2 io !MB03 E1 P$2 io *** unused *** E2 P$2 io !MB04 F1 P$2 io *** unused *** F2 P$2 io MB05 H1 P$2 io *** unused *** H2 P$2 io !MB06 J1 P$2 io *** unused *** J2 P$2 io !MB07 K1 P$2 io *** unused *** K2 P$2 io !MB08 L1 P$2 io *** unused *** L2 P$2 io !PWR_SKP M1 P$2 io *** unused *** M2 P$2 io IOP2 N1 P$2 io *** unused *** N2 P$2 io *** unused *** P1 P$2 io *** unused *** P2 P$2 io STOP_OK R1 P$2 io *** unused *** R2 P$2 io !PWR_LOW S1 P$2 io *** unused *** S2 P$2 io *** unused *** T1 P$2 io GND T2 P$2 io *** unused *** U1 P$2 io !RESTART U2 P$2 io !SHUT_DOWN V1 P$2 io *** unused *** V2 P$2 io *** unused *** AB02 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER08 AB2 AB2 in GND AC1 AC1 in ADDER09 AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER10 AF1 AF1 out ADDER11 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in !ADDER_L AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER00 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA11 AL2 AL2 out MA11 AM1 AM1 out !MA10 AM2 AM2 out MA10 AN1 AN1 out PC11 AN2 AN2 in PC_LOAD AP1 AP1 out PC10 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB11 AS2 AS2 out MB11 AT1 GND pwr GND AT2 AT2 out MB10 AU1 AU1 in AC_LOAD AU2 AU2 out !MB10 AV1 AV1 out AC11 AV2 AV2 out !AC11 BA1 BA1 out AC10 BA2 VCC pwr VCC BB1 BB1 out !AC10 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR11 BE1 BE1 in SR10 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in CARRY_INSERT BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS10 BK2 BK2 out !CARRYOUT10 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS11 BM2 BM2 in DATA10 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(5-11) BP2 BP2 in DATA11 BR1 BR1 in MEM10 BR2 BR2 in MA_ENABLE(5-11) BS1 BS1 in DATA_ADD10 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD11 BU2 BU2 in MEM_ENABLE(5-11) BV1 BV1 in MEM_ENABLE(5-11) BV2 BV2 in MEM11 AB03 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER06 AB2 AB2 in GND AC1 AC1 in ADDER07 AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER08 AF1 AF1 out ADDER09 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in ADDER10 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER11 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA09 AL2 AL2 out MA09 AM1 AM1 out !MA08 AM2 AM2 out MA08 AN1 AN1 out PC09 AN2 AN2 in PC_LOAD AP1 AP1 out PC08 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB09 AS2 AS2 out MB09 AT1 GND pwr GND AT2 AT2 out MB08 AU1 AU1 in AC_LOAD AU2 AU2 out !MB08 AV1 AV1 out AC09 AV2 AV2 out !AC09 BA1 BA1 out AC08 BA2 VCC pwr VCC BB1 BB1 out !AC08 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR09 BE1 BE1 in SR08 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in !CARRYOUT10 BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS08 BK2 BK2 out !CARRYOUT8 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS09 BM2 BM2 in DATA08 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(5-11) BP2 BP2 in DATA09 BR1 BR1 in MEM08 BR2 BR2 in MA_ENABLE(5-11) BS1 BS1 in DATA_ADD08 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD09 BU2 BU2 in MEM_ENABLE(5-11) BV1 BV1 in MEM_ENABLE(5-11) BV2 BV2 in MEM09 AB04 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER04 AB2 AB2 in GND AC1 AC1 in ADDER05 AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER06 AF1 AF1 out ADDER07 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in ADDER08 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER09 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA07 AL2 AL2 out MA07 AM1 AM1 out !MA06 AM2 AM2 out MA06 AN1 AN1 out PC07 AN2 AN2 in PC_LOAD AP1 AP1 out PC06 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB07 AS2 AS2 out MB07 AT1 GND pwr GND AT2 AT2 out MB06 AU1 AU1 in AC_LOAD AU2 AU2 out !MB06 AV1 AV1 out AC07 AV2 AV2 out !AC07 BA1 BA1 out AC06 BA2 VCC pwr VCC BB1 BB1 out !AC06 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR07 BE1 BE1 in SR06 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in !CARRYOUT8 BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS06 BK2 BK2 out !CARRYOUT6 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS07 BM2 BM2 in DATA06 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(5-11) BP2 BP2 in DATA07 BR1 BR1 in MEM06 BR2 BR2 in MA_ENABLE(5-11) BS1 BS1 in DATA_ADD06 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD07 BU2 BU2 in MEM_ENABLE(5-11) BV1 BV1 in MEM_ENABLE(5-11) BV2 BV2 in MEM07 AB05 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER02 AB2 AB2 in GND AC1 AC1 in ADDER03 AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER04 AF1 AF1 out ADDER05 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in ADDER06 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER07 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA05 AL2 AL2 out MA05 AM1 AM1 out !MA04 AM2 AM2 out MA04 AN1 AN1 out PC05 AN2 AN2 in PC_LOAD AP1 AP1 out PC04 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB05 AS2 AS2 out MB05 AT1 GND pwr GND AT2 AT2 out MB04 AU1 AU1 in AC_LOAD AU2 AU2 out !MB04 AV1 AV1 out AC05 AV2 AV2 out !AC05 BA1 BA1 out AC04 BA2 VCC pwr VCC BB1 BB1 out !AC04 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR05 BE1 BE1 in SR04 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in !CARRYOUT6 BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS04 BK2 BK2 out !CARRYOUT4 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS05 BM2 BM2 in DATA04 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(0-4) BP2 BP2 in DATA05 BR1 BR1 in MEM04 BR2 BR2 in MA_ENABLE(5-11) BS1 BS1 in DATA_ADD04 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD05 BU2 BU2 in MEM_ENABLE(0-4) BV1 BV1 in MEM_ENABLE(5-11) BV2 BV2 in MEM05 AB06 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER00 AB2 AB2 in GND AC1 AC1 in ADDER01 AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER02 AF1 AF1 out ADDER03 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in ADDER04 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER05 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA03 AL2 AL2 out MA03 AM1 AM1 out !MA02 AM2 AM2 out MA02 AN1 AN1 out PC03 AN2 AN2 in PC_LOAD AP1 AP1 out PC02 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB03 AS2 AS2 out MB03 AT1 GND pwr GND AT2 AT2 out MB02 AU1 AU1 in AC_LOAD AU2 AU2 out !MB02 AV1 AV1 out AC03 AV2 AV2 out !AC03 BA1 BA1 out AC02 BA2 VCC pwr VCC BB1 BB1 out !AC02 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR03 BE1 BE1 in SR02 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in !CARRYOUT4 BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS02 BK2 BK2 out !CARRYOUT2 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS03 BM2 BM2 in DATA02 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(0-4) BP2 BP2 in DATA03 BR1 BR1 in MEM02 BR2 BR2 in MA_ENABLE(0-4) BS1 BS1 in DATA_ADD02 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD03 BU2 BU2 in MEM_ENABLE(0-4) BV1 BV1 in MEM_ENABLE(0-4) BV2 BV2 in MEM03 AB07 AA1 AA1 in AND_ENABLE AA2 VCC pwr VCC AB1 AB1 in ADDER11 AB2 AB2 in GND AC1 AC1 in !ADDER_L AC2 GND pwr GND AD1 AD1 in DOUBLE_RIGHT_ROTATE AD2 AD2 in RIGHT_SHIFT AE1 AE1 in NO_SHIFT AE2 AE2 out ADDER00 AF1 AF1 out ADDER01 AF2 AF2 in LEFT_SHIFT AH1 AH1 in DOUBLE_LEFT_ROTATE AH2 AH2 in ADDER02 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 in ADDER03 AK1 AK1 in MA_LOAD AK2 AK2 out *** unconnected *** AL1 AL1 out !MA01 AL2 AL2 out MA01 AM1 AM1 out !MA00 AM2 AM2 out MA00 AN1 AN1 out PC01 AN2 AN2 in PC_LOAD AP1 AP1 out PC00 AP2 AP2 out *** unconnected *** AR1 AR1 in MB_LOAD AR2 AR2 out *** unconnected *** AS1 AS1 out !MB01 AS2 AS2 out MB01 AT1 GND pwr GND AT2 AT2 out MB00 AU1 AU1 in AC_LOAD AU2 AU2 out !MB00 AV1 AV1 out AC01 AV2 AV2 out !AC01 BA1 BA1 out AC00 BA2 VCC pwr VCC BB1 BB1 out !AC00 BB2 BB2 in GND BC1 BC1 in SR_ENABLE BC2 GND pwr GND BD1 BD1 in GND BD2 BD2 in SR01 BE1 BE1 in SR00 BE2 BE2 in GND BF1 BF1 in GND BF2 BF2 in GND BH1 BH1 in GND BH2 BH2 in AC_ENABLE BJ1 BJ1 in !CARRYOUT2 BJ2 BJ2 in !AC_ENABLE BK1 BK1 in INPUT_BUS00 BK2 BK2 out !CARRYOUT0 BL1 BL1 in DATA_ENABLE BL2 BL2 in IO_ENABLE BM1 BM1 in INPUT_BUS01 BM2 BM2 in DATA00 BN1 BN1 in GND BN2 BN2 in GND BP1 BP1 in MA_ENABLE(0-4) BP2 BP2 in DATA01 BR1 BR1 in MEM00 BR2 BR2 in MA_ENABLE(0-4) BS1 BS1 in DATA_ADD00 BS2 BS2 in PC_ENABLE BT1 GND pwr GND BT2 BT2 in DATA_ADD_EN BU1 BU1 in DATA_ADD01 BU2 BU2 in MEM_ENABLE(0-4) BV1 BV1 in MEM_ENABLE(0-4) BV2 BV2 in MEM01 AB29 AA2 VCC pwr VCC AC2 GND pwr GND AK2 AK in !ENABLE AM2 AM out *** unconnected *** AP2 AP out *** unconnected *** AS2 AS out SHIFT AT2 AT out !SHIFT AU2 AU out CLOCK1 BA2 VCC pwr VCC BB2 -15V pwr B29B2 BC2 GND pwr GND BP2 BP in RDR_FEED_SW BR2 BR out STOP_COMPLETE BS2 BS in !HSR_RUN AB30 AA2 VCC pwr VCC AC2 GND pwr GND AD1 AD1 in RD_HOLE2 AD2 AD2 in RD_HOLE1 AE1 AE1 in RD_HOLE4 AE2 AE2 in RD_HOLE3 AF1 AF1 in RD_HOLE8 AF2 AF2 in RD_HOLE7 AH1 AH1 in RD_HOLE6 AH2 AH2 in RD_HOLE5 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 out *** unconnected *** AK1 AK1 out !HSR_RUN AK2 AK2 oc !RDR_SKP AL2 AL2 oc !RDR_INT AM2 AM2 out *** unconnected *** AN1 AN1 oc !INT_IO_BUS11 AN2 AN2 oc !INT_IO_BUS7 AP1 AP1 oc !INT_IO_BUS9 AP2 AP2 oc !INT_IO_BUS4 AR1 AR1 oc !INT_IO_BUS6 AR2 AR2 oc !INT_IO_BUS10 AS1 AS1 oc !INT_IO_BUS8 AS2 AS2 oc !INT_IO_BUS5 AT1 GND pwr GND AT2 AT2 out *** unconnected *** AU2 AU2 in IOP1 AV2 AV2 in IOP2 BA2 VCC pwr VCC BC2 GND pwr GND BD1 BD1 in !SHIFT BD2 BD2 in !MB03 BE1 BE1 in !MB05 BE2 BE2 in !MB04 BF1 BF1 in !MB07 BF2 BF2 in !MB06 BH2 BH2 in MB08 BJ1 BJ1 in SHIFT BK1 BK1 in IOP4 BK2 BK2 out !ENABLE BM1 BM1 in RDR_FEED_SW BM2 BM2 in FEED_HOLE BN2 BN2 in STOP_COMPLETE BP1 BP1 in !INITIALIZE BP2 BP2 out !A BR1 BR1 out !B BR2 BR2 out PWR BS1 BS1 out A BS2 BS2 in CLOCK1 BT1 GND pwr GND BU2 BU2 out B AB31 AA2 VCC pwr VCC AC2 GND pwr GND AD1 AD1 in AC10 AD2 AD2 in AC11 AE1 AE1 in AC08 AE2 AE2 in AC09 AF1 AF1 in AC06 AF2 AF2 in AC07 AH1 AH1 in AC04 AH2 AH2 in AC05 AJ1 AJ1 out *** unconnected *** AJ2 AJ2 out *** unconnected *** AK1 AK1 out PB0 AK2 AK2 out PB4 AL1 AL1 out PB1 AL2 AL2 out PB5 AM1 AM1 out PB2 AM2 AM2 out PB6 AN1 AN1 out PB3 AN2 AN2 out PB7 AP2 AP2 in IOP4 AR1 AR1 in IOP2 AR2 AR2 in IOP1 AS1 AS1 out *** unconnected *** AS2 AS2 in !INITIALIZE AT1 GND pwr GND AT2 AT2 in C34E1 AU1 AU1 in B31V1 AU2 AU2 out *** unconnected *** AV2 AV2 in C34D1 BA2 VCC pwr VCC BC2 GND pwr GND BD1 BD1 in !MB04 BD2 BD2 in !MB05 BE1 BE1 in !MB06 BE2 BE2 in MB07 BF1 BF1 in !MB08 BF2 BF2 in !MB03 BH2 BH2 out !RDR_DONE BN2 BN2 oc !RDR_SKP BS2 BS2 oc !RDR_INT BT1 GND pwr GND BU2 P$1 pas B31U2 BV1 BV1 out B31V1 B01 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io PC00 C2 P$2 io GND D1 P$2 io PC01 D2 P$2 io !AC04 E1 P$2 io PC02 E2 P$2 io !AC05 F1 P$2 io PC03 F2 P$2 io !MB05 H1 P$2 io PC04 H2 P$2 io !MA05 J1 P$2 io PC05 J2 P$2 io !AC06 K1 P$2 io *** unused *** K2 P$2 io !AC07 L1 P$2 io *** unused *** L2 P$2 io !MB06 M1 P$2 io *** unused *** M2 P$2 io !MA06 N1 P$2 io *** unused *** N2 P$2 io PANEL_LOCK P1 P$2 io *** unused *** P2 P$2 io !MA07 R1 P$2 io *** unused *** R2 P$2 io !MB07 S1 P$2 io *** unused *** S2 P$2 io !MB08 T1 P$2 io GND T2 P$2 io !MA08 U1 P$2 io *** unused *** U2 P$2 io !AC08 V1 P$2 io B01_10V V2 P$2 io !AC09 B08 A1 IN1 in !KEY_CONT A2 VCC pwr VCC B1 IN2 in MFTP0 C1 IN3 in MFTP0 C2 GND pwr GND D1 IN4 in MFTP0 D2 IN1 in A13R1 E1 OUT oc !MANUAL_PRESET E2 IN2 in A13R1 F1 IN1 in !AND_ENABLE F2 IN3 in A13R1 H1 IN2 in !AND_ENABLE H2 IN4 in !SET_IO_ON J1 IN3 in !AND_ENABLE J2 OUT oc PC_LOAD K1 IN4 in !AND_ENABLE K2 IN1 in +3V(10) L1 OUT oc AND_ENABLE L2 IN2 in +3V(10) M1 IN1 in C05S2 M2 IN3 in !TP2 N1 IN2 in C05S2 N2 IN4 in !TP2 P1 IN3 in !TP4 P2 OUT oc MB_LOAD R1 IN4 in !TP4 R2 IN1 in C12M2 S1 OUT oc MA_LOAD S2 IN2 in B13N1 T1 GND pwr GND T2 IN3 in !GO U1 P$1 pas +3V(10) U2 IN4 in !OP_STROBE V1 P$1 pas +3V(12) V2 OUT oc AC_LOAD B09 A1 IN1 in FETCH A2 VCC pwr VCC B1 IN2 in FETCH C1 IN3 in FETCH C2 GND pwr GND D1 IN4 in FETCH D2 IN1 in !DOUBLE_RIGHT_ROTATE E1 OUT oc B_FETCH E2 IN2 in !DOUBLE_RIGHT_ROTATE F1 IN1 in EXECUTE F2 IN3 in !DOUBLE_RIGHT_ROTATE H1 IN2 in EXECUTE H2 IN4 in !DOUBLE_RIGHT_ROTATE J1 IN3 in EXECUTE J2 OUT oc DOUBLE_RIGHT_ROTATE K1 IN4 in EXECUTE K2 IN1 in !LEFT_SHIFT L1 OUT oc B_EXECUTE L2 IN2 in !LEFT_SHIFT M1 IN1 in !RIGHT_SHIFT M2 IN3 in !LEFT_SHIFT N1 IN2 in !RIGHT_SHIFT N2 IN4 in !LEFT_SHIFT P1 IN3 in !RIGHT_SHIFT P2 OUT oc LEFT_SHIFT R1 IN4 in !RIGHT_SHIFT R2 IN1 in !DOUBLE_LEFT_ROTATE S1 OUT oc RIGHT_SHIFT S2 IN2 in !DOUBLE_LEFT_ROTATE T1 GND pwr GND T2 IN3 in !DOUBLE_LEFT_ROTATE U1 P$1 pas +3V(7) U2 IN4 in !DOUBLE_LEFT_ROTATE V1 P$1 pas +3V(11) V2 OUT oc DOUBLE_LEFT_ROTATE B10 A1 IN1A in +3V(12) A2 VCC pwr VCC B1 IN1B in ADDER11 C1 IN1C in +3V(12) C2 GND pwr GND D1 IN1D in RIGHT_SHIFT D2 IN1A in +3V(7) E1 IN2A in ADDER10 E2 IN1B in TS3 F1 IN2B in DOUBLE_RIGHT_ROTATE F2 IN1C in B_EXECUTE H1 IN3A in !ADDER_L H2 IN1D in JMS J1 IN3B in NO_SHIFT J2 IN2A in TS1 K1 IN4A in ADDER00 K2 IN2B in B_FETCH L1 IN4B in LEFT_SHIFT L2 IN3A in MFTS2 M1 IN5A in ADDER01 M2 IN3B in KEY_EX+DP N1 IN5B in DOUBLE_LEFT_ROTATE N2 IN4A in TS4 P1 IN5C in +3V(12) P2 IN4B in B_WC R1 OUT out B10R1 R2 IN4C in +3V(7) S1 IN1A in A10V2 S2 IN4D in +3V(7) T1 GND pwr GND T2 OUT out !MA_ENABLE(5-11) U1 IN1B in CARRYOUT0 U2 IN2B in !CARRYOUT0 V1 IN2A in B12B1 V2 OUT out !ADDER_L B11 A1 R in +3V(11) A2 VCC pwr VCC B1 C in B12L2 C1 D in !MB11 C2 GND pwr GND D1 S in B12J2 D2 C in B12F2 E1 1 out !INT_ENABLE E2 D in !INT_ENABLE F1 0 out INT_ENABLE F2 S in INT_ENABLE H1 C in INT_STROBE H2 1 out *** unconnected *** J1 D in C28H2 J2 0 out INT_DELAY K1 S in !MANUAL_PRESET K2 R in +3V(11) L1 1 out *** unconnected *** L2 C in AC_LOAD M1 0 out INT_SYNC M2 D in B10R1 N1 C in A11V1 N2 S in +3V(11) P1 D in A13T2 P2 1 out LINK R1 S in !PC_LOAD R2 0 out !LINK S1 1 out !SKIP S2 C in TP1 T1 GND pwr GND T2 D in !BRK_RQST U1 0 out SKIP U2 S in !MANUAL_PRESET V1 0 out SYNC V2 1 out *** unconnected *** B12 A1 IN in A10V2 A2 VCC pwr VCC B1 OUT out B12B1 C1 IN in !CARRYOUT0 C2 GND pwr GND D1 IN in MEM_ENABLE(0-4) D2 OUT out CARRYOUT0 E1 OUT out !MEM_ENABLE(0-4) E2 IN in C14S2 F1 IN in !!L_ENABLE F2 OUT out B12F2 H1 OUT out !L_ENABLE H2 IN in B13S2 J1 IN in !BADDR03 J2 OUT out B12J2 K1 OUT out DATA_ADD03 K2 IN in C13P2 L1 IN in B14J2 L2 OUT out B12L2 M1 OUT out B12M1 M2 IN in !INT_OK N1 IN in !JMP_DIRECT N2 OUT out INT_OK P1 OUT out JMP_DIRECT P2 IN in B14V2 R1 IN in B14P2 R2 OUT out CONTROL_IOT S1 OUT out B12S1 S2 IN in C14K2 T1 GND pwr GND T2 OUT out B12T2 U1 OUT out B12U1 U2 IN in TP4 V1 IN in C13S1 V2 OUT out !TP4 B13 A1 IN1 in !D_SET A2 VCC pwr VCC B1 IN2 in !E_SET C1 OUT out B13C1 C2 GND pwr GND D1 IN1 in TS4 D2 IN1 in KEY_LA E1 IN2 in F_SET E2 IN2 in C15F1 F1 OUT out !PC_ENABLE F2 OUT out B13F2 H1 IN1 in OP1 H2 IN1 in OP1 J1 IN2 in MB07 J2 IN2 in MB06 K1 OUT out !!L_ENABLE K2 OUT out !!AC_ENABLE L1 IN1 in IO_STROBE L2 IN1 in A11S2 M1 IN2 in IO_ENABLE M2 IN2 in !PROTECT N1 OUT out B13N1 N2 OUT out CARRY_INSERT P1 IN1 in *** unused *** P2 IN1 in B13V2 R1 IN2 in *** unused *** R2 IN2 in !GO S1 OUT out *** unused *** S2 OUT out B13S2 T1 GND pwr GND T2 IN1 in TP1 U1 P$1 pas *** unused *** U2 IN2 in INT_OK V1 P$1 pas *** unused *** V2 OUT out B13V2 B14 A1 IN1 in !MA00 A2 VCC pwr VCC B1 IN2 in !MA01 C1 IN3 in !MA02 C2 GND pwr GND D1 IN4 in !MA03 D2 IN5 in !MA04 E2 IN6 in !MA05 F1 IN1 in !AC00 F2 IN7 in !MA06 H1 IN2 in !AC01 H2 IN8 in !MA07 J1 IN3 in !AC02 J2 OUT out B14J2 K1 IN4 in !AC03 K2 IN5 in !AC04 L2 IN6 in !AC05 M1 IN1 in IOT M2 IN7 in !AC06 N1 IN2 in !MB03 N2 IN8 in !AC07 P1 IN3 in !MB04 P2 OUT out B14P2 R1 IN4 in !MB05 R2 IN5 in !MB06 S2 IN6 in !MB07 T1 GND pwr GND T2 IN7 in !MB08 U1 P$1 pas +3V(17) U2 IN8 in +3V(17) V1 P$1 pas *** unused *** V2 OUT out B14V2 B15 A1 IN1 in IOP4 A2 VCC pwr VCC B1 IN2 in IOP4 C1 IN3 in !MB08 C2 GND pwr GND D1 IN4 in !MB07 D2 IN5 in !MB06 E2 IN6 in MB05 F1 IN1 in !MP_INT F2 IN7 in !MB04 H1 IN2 in IOP1 H2 IN8 in !MB03 J1 IN3 in !MB08 J2 OUT out !CLR_PARITY_ERROR K1 IN4 in !MB07 K2 IN5 in !MB06 L2 IN6 in MB05 M1 IN1 in *** unused *** M2 IN7 in !MB04 N1 IN2 in *** unused *** N2 IN8 in !MB03 P1 IN3 in *** unused *** P2 OUT out !MP_SKIP R1 IN4 in *** unused *** R2 IN5 in *** unused *** S2 IN6 in *** unused *** T1 GND pwr GND T2 IN7 in *** unused *** U1 P$1 pas B15U1 U2 IN8 in *** unused *** V1 P$1 pas *** unused *** V2 OUT out *** unused *** B16 A1 1B in !MB00 A2 VCC pwr VCC B1 2B in !MB01 C1 4B in !MB02 C2 GND pwr GND D1 8B in !MB03 E1 1A in MB00 F1 2A in MB01 H1 4A in MB02 J1 8A in MB03 K1 ODD out B16K1 K2 1B in !MB08 L1 EVEN out B16L1 L2 2B in !MB09 M2 4B in !MB10 N2 8B in !MB11 P2 1A in MB08 R2 2A in MB09 S2 4A in MB10 T1 GND pwr GND T2 8A in MB11 U2 ODD out B16U2 V2 EVEN out B16V2 B17 A1 1B in B16L1 A2 VCC pwr VCC B1 2B in B17V2 C1 4B in B16V2 C2 GND pwr GND D1 8B in B15U1 E1 1A in B16K1 F1 2A in B17U2 H1 4A in B16U2 J1 8A in GND K1 ODD out MB_PARITY_ODD K2 1B in !MB04 L1 EVEN out *** unconnected *** L2 2B in !MB05 M2 4B in !MB06 N2 8B in !MB07 P2 1A in MB04 R2 2A in MB05 S2 4A in MB06 T1 GND pwr GND T2 8A in MB07 U2 ODD out B17U2 V2 EVEN out B17V2 B18 A1 A1 oc MEM06 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in B21C2 E1 E1 out *** unconnected *** E2 E2 in B21D2 K2 K2 out *** unconnected *** L1 L1 in B21E2 M1 M1 in B21F2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM07 B19 A1 A1 oc MEM08 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in B21H2 E1 E1 out *** unconnected *** E2 E2 in B21J2 K2 K2 out *** unconnected *** L1 L1 in B21K2 M1 M1 in B21L2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM09 B20 A1 A1 oc MEM10 A2 VCC pwr VCC B1 B1 in !MEM_BEGIN B2 -15V pwr -15V C1 C1 out *** unconnected *** C2 GND pwr GND D1 D1 in STROBE_FIELD0 D2 D2 in B21M2 E1 E1 out *** unconnected *** E2 E2 in B21N2 K2 K2 out *** unconnected *** L1 L1 in B21P2 M1 M1 in B21R2 R1 R1 in STROBE_FIELD0 S1 S1 out *** unconnected *** S2 S2 pas SLICE T1 GND pwr GND T2 T2 in B_MEM_ENABLE U2 U2 oc MEM11 B21 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io B21C2 D2 P$2 io B21D2 E2 P$2 io B21E2 F2 P$2 io B21F2 H2 P$2 io B21H2 J2 P$2 io B21J2 K2 P$2 io B21K2 L2 P$2 io B21L2 M2 P$2 io B21M2 N2 P$2 io B21N2 P2 P$2 io B21P2 R2 P$2 io B21R2 S2 P$2 io *** unused *** T2 P$2 io *** unused *** U2 P$2 io *** unused *** V2 P$2 io *** unused *** B22 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io B23S2 D2 P$2 io B23T2 E2 P$2 io B23P1 F2 P$2 io B23R1 H2 P$2 io B24J2 J2 P$2 io B24K2 K2 P$2 io B24H1 L2 P$2 io B24J1 M2 P$2 io B24S2 N2 P$2 io B24T2 P2 P$2 io B24P1 R2 P$2 io B24R1 S2 P$2 io B22S2 T2 P$2 io B22T2 U2 P$2 io *** unused *** V2 P$2 io *** unused *** B23 A1 A1 in B_INHIBIT A2 VCC pwr VCC C2 GND pwr GND D1 D1 in !MA05 D2 D2 in !MA04 E1 E1 pas B23E1 E2 E2 in B_MEM_ENABLE F1 H in B25R2 F2 F2 pas B23F2 H1 J pas B23H1 H2 H in B25P2 J1 K pas B23J1 J2 J pas B23J2 K1 K1 pas MEM_SUPPLY+ K2 K pas B23K2 L1 L1 in !MA07 L2 L2 pas MEM_SUPPLY+ M1 M1 pas B23M1 M2 M2 in !MA06 N1 H in B25T2 N2 N2 in B_MEM_ENABLE P1 J pas B23P1 P2 P2 pas B23P2 R1 K pas B23R1 R2 H in B25S2 S1 S1 pas MEM_SUPPLY+ S2 J pas B23S2 T1 GND pwr GND T2 K pas B23T2 U2 U2 pas MEM_SUPPLY+ V2 V2 in MEM_SUPPLY- B24 A1 A1 in B_INHIBIT A2 VCC pwr VCC C2 GND pwr GND D1 D1 in !MB09 D2 D2 in !MB08 E1 E1 pas B24E1 E2 E2 in B_MEM_ENABLE F1 H in B26R2 F2 F2 pas B24F2 H1 J pas B24H1 H2 H in B26P2 J1 K pas B24J1 J2 J pas B24J2 K1 K1 pas MEM_SUPPLY+ K2 K pas B24K2 L1 L1 in !MB11 L2 L2 pas MEM_SUPPLY+ M1 M1 pas B24M1 M2 M2 in !MB10 N1 H in B26T2 N2 N2 in B_MEM_ENABLE P1 J pas B24P1 P2 P2 pas B24P2 R1 K pas B24R1 R2 H in B26S2 S1 S1 pas MEM_SUPPLY+ S2 J pas B24S2 T1 GND pwr GND T2 K pas B24T2 U2 U2 pas MEM_SUPPLY+ V2 V2 in MEM_SUPPLY- B25 B2 P$1 pas MEM_RET C2 P$2 pas *** unused *** D2 P$2 pas Y_R/W_SOURCE E2 P$2 pas MEM_SUPPLY+ F2 P$1 pas B25F2 H2 P$1 pas MEM_SUPPLY- J2 P$3 pas MEM_SUPPLY- K2 P$1 pas B23M1 L2 P$1 pas B23P2 M2 P$1 pas B23E1 N2 P$1 pas B23F2 P2 P$2 pas B25P2 R2 P$2 pas B25R2 S2 P$2 pas B25S2 T2 P$2 pas B25T2 U2 P$2 pas MEM_SUPPLY- V2 P$1 pas *** unused *** B26 B2 P$1 pas MEM_RET C2 P$2 pas *** unused *** D2 P$2 pas X_R/W_RETURN E2 P$2 pas GND F2 P$1 pas B26F2 H2 P$1 pas MEM_SUPPLY+ J2 P$3 pas MEM_SUPPLY- K2 P$1 pas B24M1 L2 P$1 pas B24P2 M2 P$1 pas B24E1 N2 P$1 pas B24F2 P2 P$2 pas B26P2 R2 P$2 pas B26R2 S2 P$2 pas B26S2 T2 P$2 pas B26T2 U2 P$2 pas MEM_SUPPLY- V2 P$1 pas *** unused *** B27 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io *** unused *** D2 P$2 io *** unused *** E2 P$2 io *** unused *** F2 P$2 io B36S2 H2 P$2 io *** unused *** J2 P$2 io B27K2 K2 P$2 io B27K2 L2 P$2 io *** unused *** M2 P$2 io MEM_SUPPLY+ N2 P$2 io *** unused *** P2 P$2 io *** unused *** R2 P$2 io B22S2 S2 P$2 io B22T2 T2 P$2 io *** unused *** U2 P$2 io *** unused *** V2 P$2 io MEM_SUPPLY- B28 A2 P$2 io VCC B2 P$2 io B29B2 C2 P$2 io GND D2 P$2 io GND E2 P$2 io GND F2 P$2 io GND H2 P$2 io GND J2 P$2 io B27K2 K2 P$2 io B27K2 L2 P$2 io MEM_RET M2 P$2 io MEM_SUPPLY+ N2 P$2 io MEM_SUPPLY+ P2 P$2 io MEM_SUPPLY+ R2 P$2 io MEM_SUPPLY+ S2 P$2 io MEM_SUPPLY- T2 P$2 io MEM_SUPPLY- U2 P$2 io MEM_SUPPLY- V2 P$2 io MEM_SUPPLY- B32 A1 GND pwr GND A2 VCC pwr VCC B1 P$1 pas !BADDR00 C1 GND pwr GND C2 GND pwr GND D1 P$1 pas !BADDR01 D2 P$1 pas !BADDR09 E1 P$1 pas !BADDR02 E2 P$1 pas !BADDR10 F1 GND pwr GND F2 GND pwr GND H1 P$1 pas !BADDR03 H2 P$1 pas !BADDR11 J1 P$1 pas !BADDR04 J2 GND pwr GND K1 GND pwr GND K2 P$1 pas *** unused *** L1 P$1 pas !BADDR05 L2 GND pwr GND M1 P$1 pas !BADDR06 M2 P$1 pas DATA_IN N1 GND pwr GND N2 GND pwr GND P1 P$1 pas !BADDR07 P2 P$1 pas !BBREAK R1 GND pwr GND R2 GND pwr GND S1 P$1 pas !BADDR08 S2 P$1 pas !BADD_ACCEPTED T1 GND pwr GND T2 P$1 pas *** unused *** U2 GND pwr GND V2 P$1 pas BINITIALIZE2 B33 A1 GND pwr GND A2 VCC pwr VCC B1 P$1 pas !BDATA00 C1 GND pwr GND C2 GND pwr GND D1 P$1 pas !BDATA01 D2 P$1 pas !BDATA09 E1 P$1 pas !BDATA02 E2 P$1 pas !BDATA10 F1 GND pwr GND F2 GND pwr GND H1 P$1 pas !BDATA03 H2 P$1 pas !BDATA11 J1 P$1 pas !BDATA04 J2 GND pwr GND K1 GND pwr GND K2 P$1 pas !3CYCLE L1 P$1 pas !BDATA05 L2 GND pwr GND M1 P$1 pas !BDATA06 M2 P$1 pas CA_INCREMENT N1 GND pwr GND N2 GND pwr GND P1 P$1 pas !BDATA07 P2 P$1 pas WC_OVERFLOW R1 GND pwr GND R2 GND pwr GND S1 P$1 pas !BDATA08 S2 P$1 pas !EXT_ADD2 T1 GND pwr GND T2 P$1 pas *** unused *** U2 GND pwr GND V2 P$1 pas *** unused *** B34 A1 GND pwr GND B1 P$2 io !EA C1 GND pwr GND C2 GND pwr GND D1 P$2 io MMA00 D2 P$2 io MMA08 E1 P$2 io MMA01 E2 P$2 io MMA09 F1 GND pwr GND F2 GND pwr GND H1 P$2 io MMA02 H2 P$2 io MMA10 J1 P$2 io MMA03 J2 GND pwr GND K1 GND pwr GND K2 P$2 io MMA11 L1 P$2 io MMA04 L2 GND pwr GND M1 P$2 io MMA05 M2 P$2 io *** unused *** N1 GND pwr GND N2 GND pwr GND P1 P$2 io MMA06 P2 P$2 io MEM_START R1 GND pwr GND R2 GND pwr GND S1 P$2 io MMA07 S2 P$2 io !STROBE T1 GND pwr GND T2 P$2 io BTP2 U2 GND pwr GND V2 P$2 io !MEM_DONE B35 A1 GND pwr GND B1 P$2 io MEM_P C1 GND pwr GND C2 GND pwr GND D1 P$2 io MEM00 D2 P$2 io MEM08 E1 P$2 io MEM01 E2 P$2 io MEM09 F1 GND pwr GND F2 GND pwr GND H1 P$2 io MEM02 H2 P$2 io MEM10 J1 P$2 io MEM03 J2 GND pwr GND K1 GND pwr GND K2 P$2 io MEM11 L1 P$2 io MEM04 L2 GND pwr GND M1 P$2 io MEM05 M2 P$2 io *** unused *** N1 GND pwr GND N2 GND pwr GND P1 P$2 io MEM06 P2 P$2 io *** unused *** R1 GND pwr GND R2 GND pwr GND S1 P$2 io MEM07 S2 P$2 io *** unused *** T1 GND pwr GND T2 P$2 io BEMA U2 GND pwr GND V2 P$2 io !EMA B36 A1 GND pwr GND B1 P$2 io B36B1 C1 GND pwr GND C2 GND pwr GND D1 P$2 io B36D1 D2 P$2 io B36D2 E1 P$2 io B36E1 E2 P$2 io B36E2 F1 GND pwr GND F2 GND pwr GND H1 P$2 io BTP3 H2 P$2 io B36H2 J1 P$2 io B36J1 J2 GND pwr GND K1 GND pwr GND K2 P$2 io *** unused *** L1 P$2 io !INT_INHIBIT L2 GND pwr GND M1 P$2 io B36M1 M2 P$2 io *** unused *** N1 GND pwr GND N2 GND pwr GND P1 P$2 io B36P1 P2 P$2 io *** unused *** R1 GND pwr GND R2 GND pwr GND S1 P$2 io B36S1 S2 P$2 io B36S2 T1 GND pwr GND T2 P$2 io B36T2 U2 GND pwr GND V2 P$2 io B36V2 C01 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io !MB09 D2 P$2 io *** unused *** E1 P$2 io !MA09 E2 P$2 io SR09 F1 P$2 io !AC11 F2 P$2 io SR10 H1 P$2 io !AC10 H2 P$2 io SR08 J1 P$2 io !MA10 J2 P$2 io SR07 K1 P$2 io !MB10 K2 P$2 io SR06 L1 P$2 io *** unused *** L2 P$2 io SR05 M1 P$2 io *** unused *** M2 P$2 io !MB11 N1 P$2 io *** unused *** N2 P$2 io !MA11 P1 P$2 io *** unused *** P2 P$2 io !FETCH R1 P$2 io *** unused *** R2 P$2 io !IR0 S1 P$2 io *** unused *** S2 P$2 io !INT_ENABLE T1 P$2 io GND T2 P$2 io *** unused *** U1 P$2 io *** unused *** U2 P$2 io !EXECUTE V1 P$2 io C01_10V V2 P$2 io !IR1 C02 A1 IN1 in !KEY_ST A2 VCC pwr VCC B1 IN2 in !RESTART C1 OUT out KEY_ST C2 GND pwr GND D1 IN1 in !KEY_DP D2 IN1 in !ILLEGAL_REF E1 IN2 in !KEY_EX E2 IN2 in !KEY_SS F1 OUT out KEY_EX+DP F2 OUT out KEY_SS+I_REF H1 IN1 in !KEY_STOP H2 IN1 in !KEY_EX+DP J1 IN2 in +3V(1) J2 IN2 in !KEY_LA K1 OUT out KEY_STOP K2 OUT out KEY_LA+EX+DP L1 IN1 in MFTP2 L2 IN1 in C02N1 M1 IN2 in +3V(1) M2 IN2 in D04D1 N1 OUT out C02N1 N2 OUT out MEM_START P1 IN1 in D04D1 P2 IN1 in MFTP2 R1 IN2 in C02S2 R2 IN2 in KEY_CONT S1 OUT out TP4 S2 OUT out C02S2 T1 GND pwr GND T2 IN1 in MFTP0 U1 P$1 pas +3V(1) U2 IN2 in KEY_ST V1 P$1 pas *** unused *** V2 OUT out C02V2 C04 A1 R in !STROBE A2 VCC pwr VCC B1 C in TP4 C1 D in +3V(1) C2 GND pwr GND D1 S in !MANUAL_PRESET D2 C in GND E1 1 out TS1 E2 D in GND F1 0 out !TS1 F2 S in !MEM_DONE H1 C in D05F1 H2 1 out MEM_IDLE J1 D in GND J2 0 out *** unconnected *** K1 S in !IO_START K2 R in !MANUAL_PRESET L1 1 out PAUSE L2 C in TP2 M1 0 out !PAUSE M2 D in GND N1 C in TP3 N2 S in !STROBE P1 D in GND P2 1 out TS2 R1 S in !TP2 R2 0 out *** unconnected *** S1 1 out TS3 S2 C in TP4 T1 GND pwr GND T2 D in GND U1 0 out !TS3 U2 S in !INT_STROBE V1 0 out !TS4 V2 1 out TS4 C05 A1 IN1 in TP3 A2 VCC pwr VCC B1 IN2 in !IOT C1 OUT out C05C1 C2 GND pwr GND D1 IN1 in C05C1 D2 IN1 in TP3 E1 IN2 in !IO_END E2 IN2 in IOT F1 OUT out INT_STROBE F2 OUT out !IO_START H1 IN1 in IO_STROBE H2 IN1 in IO_STROBE J1 IN2 in IOP_C J2 IN2 in !IOP_C K1 OUT out !IO_END K2 OUT out !IO_RECYCLE L1 IN1 in C02V2 L2 IN1 in SET_IO_ON M1 IN2 in !POWER_CLEAR M2 IN2 in SET_IO_ON N1 OUT out INITIALIZE N2 OUT out !SET_IO_ON P1 IN1 in !IO_RECYCLE P2 IN1 in MFTP1 R1 IN2 in !IO_START R2 IN2 in !KEY_CONT S1 OUT out C05S1 S2 OUT out C05S2 T1 GND pwr GND T2 IN1 in !RESTART U1 P$1 pas +3V(2) U2 IN2 in !KEY_LA V1 P$1 pas +3V(3) V2 OUT out C05V2 C06 A1 R in !INITIALIZE A2 VCC pwr VCC B1 C in !IO_ROT C1 D in IOP_C C2 GND pwr GND D1 S in +3V(2) D2 C in !IO_ROT E1 1 out IOP_A E2 D in !IOP_B F1 0 out !IOP_A F2 S in +3V(2) H1 C in IO_STROBE H2 1 out !IOP_C J1 D in GND J2 0 out IOP_C K1 S in !SET_IO_ON K2 R in +3V(2) L1 1 out IO_ON L2 C in !IO_ROT M1 0 out *** unconnected *** M2 D in !IOP_A N1 C in TP3 N2 S in !INITIALIZE P1 D in C07B1 P2 1 out !IOP_B R1 S in !POWER_CLEAR R2 0 out IOP_B S1 1 out !RUN S2 C in TP2 T1 GND pwr GND T2 D in !PROTECT U1 0 out RUN U2 S in !MANUAL_PRESET V1 0 out *** unconnected *** V2 1 out !ILLEGAL_REF C07 A1 IN in D09R1 A2 VCC pwr VCC B1 OUT out C07B1 C1 IN in D12K1 C2 GND pwr GND D1 IN in !AND D2 OUT out C07D2 E1 OUT out AND E2 IN in !OP1 F1 IN in !TAD F2 OUT out OP1 H1 OUT out TAD H2 IN in !OP2 J1 IN in !ISZ J2 OUT out OP2 K1 OUT out ISZ K2 IN in C10V2 L1 IN in !DCA L2 OUT out C07L2 M1 OUT out DCA M2 IN in !F_SET N1 IN in !JMS N2 OUT out F_SET P1 OUT out JMS P2 IN in !D_SET R1 IN in !JMP R2 OUT out D_SET S1 OUT out JMP S2 IN in E_SET T1 GND pwr GND T2 OUT out !E_SET U1 OUT out IOT U2 IN in !BREAK V1 IN in !IOT V2 OUT out B_BK C08 A1 R in D12K2 A2 VCC pwr VCC B1 C in C07D2 C1 D in D13S1 C2 GND pwr GND D1 S in +3V(3) D2 C in C07D2 E1 1 out !IR0 E2 D in MEM01 F1 0 out IR0 F2 S in +3V(3) H1 C in C07D2 H2 1 out IR1 J1 D in MEM02 J2 0 out !IR1 K1 S in +3V(3) K2 R in !MANUAL_PRESET L1 1 out IR2 L2 C in TP4 M1 0 out !IR2 M2 D in F_SET N1 C in TP4 N2 S in !GO P1 D in D_SET P2 1 out FETCH R1 S in +3V(3) R2 0 out !FETCH S1 1 out DEFER S2 C in TP4 T1 GND pwr GND T2 D in E_SET U1 0 out !DEFER U2 S in +3V(3) V1 0 out !EXECUTE V2 1 out EXECUTE C09 A1 IN1 in !IR0 A2 VCC pwr VCC B1 IN2 in !IR1 C1 IN3 in IR2 C2 GND pwr GND D1 OUT out !TAD D2 IN1 in !IR0 E1 IN1 in !IR0 E2 IN2 in !IR1 F1 IN2 in IR1 F2 IN3 in !IR2 H1 IN3 in !IR2 H2 OUT out !AND J1 OUT out !ISZ J2 IN1 in !IR0 K1 IN1 in IR0 K2 IN2 in IR1 L1 IN2 in !IR1 L2 IN3 in IR2 M1 IN3 in !IR2 M2 OUT out !DCA N1 OUT out !JMS N2 IN1 in !(IOT+OPR) P1 IN1 in IR0 P2 IN2 in B_FETCH R1 IN2 in !IR1 R2 IN3 in MB03 S1 IN3 in IR2 S2 OUT out !D_SET T1 GND pwr GND T2 IN1 in !INT_OK U1 OUT out !JMP U2 IN2 in D12F1 V1 OUT out E_SET V2 IN3 in C11L1 C10 A1 IN1 in IR0 A2 VCC pwr VCC B1 IN2 in IR1 C1 IN3 in IR2 C2 GND pwr GND D1 IN4 in B_FETCH D2 IN5 in TS3 E2 IN6 in !MB03 F1 IN1 in IR0 F2 IN7 in +3V(5) H1 IN2 in IR1 H2 IN8 in +3V(5) J1 IN3 in IR2 J2 OUT out !OP1 K1 IN4 in B_FETCH K2 IN5 in TS3 L2 IN6 in MB03 M1 IN1 in +3V(5) M2 IN7 in !MB11 N1 IN2 in MA00 N2 IN8 in +3V(5) P1 IN3 in MA01 P2 OUT out !OP2 R1 IN4 in MA02 R2 IN5 in MA03 S2 IN6 in MA04 T1 GND pwr GND T2 IN7 in BEMA U1 P$1 pas +3V(5) U2 IN8 in KEY_PROTECT V1 P$1 pas *** unused *** V2 OUT out C10V2 C11 A1 IN1 in !SPECIAL_CYCLE A2 VCC pwr VCC B1 IN2 in !BREAK_OK C1 IN3 in !E_SET C2 GND pwr GND D1 IN4 in !D_SET D2 IN1 in !E_SET E1 OUT out !F_SET E2 IN2 in SYNC F1 IN1 in !(IOT+OPR) F2 IN3 in !SPECIAL_CYCLE H1 IN2 in B_FETCH H2 IN4 in !D_SET J1 IN3 in !JMP J2 OUT out !BREAK_OK K1 IN4 in !MB03 K2 IN1 in TS2 L1 OUT out C11L1 L2 IN2 in !PROTECT M1 IN1 in IR0 M2 IN3 in B_BK N1 IN2 in IR1 N2 IN4 in DATA_IN P1 IN3 in !IR2 P2 OUT out !DATA_ENABLE R1 IN4 in B_FETCH R2 IN1 in TS2 S1 OUT out !IOT S2 IN2 in B_EXECUTE T1 GND pwr GND T2 IN3 in !PROTECT U1 P$1 pas *** unused *** U2 IN4 in JMS V1 P$1 pas *** unused *** V2 OUT out !INT_SKIP_EN C12 A1 IN1 in TAD A2 VCC pwr VCC B1 IN2 in TS3 C1 IN3 in B_EXECUTE C2 GND pwr GND D1 OUT out !ADD D2 IN1 in OP2 E1 IN1 in MEM_ENABLE(5-11) E2 IN2 in !MB11 F1 IN2 in !MEM_ENABLE(0-4) F2 IN3 in MB09 H1 IN3 in MB04 H2 OUT out C12H2 J1 OUT out C12J1 J2 IN1 in TP3 K1 IN1 in !RESTART K2 IN2 in C12S2 L1 IN2 in MFTS1 L2 IN3 in B_EXECUTE M1 IN3 in KEY_ST+EX+DP M2 OUT out C12M2 N1 OUT out C12N1 N2 IN1 in !AND P1 IN1 in KEY_DP P2 IN2 in !TAD R1 IN2 in !PROTECT R2 IN3 in !DCA S1 IN3 in MFTS3 S2 OUT out C12S2 T1 GND pwr GND T2 IN1 in IO_STROBE U1 OUT out C12U1 U2 IN2 in IO_ENABLE V1 OUT out C12V1 V2 IN3 in !SKIP C13 A1 IN1 in TS3 A2 VCC pwr VCC B1 IN2 in JMP C1 IN3 in B_FETCH C2 GND pwr GND D1 IN4 in !MB03 D2 IN1 in INT_DELAY E1 OUT out !JMP_DIRECT E2 IN2 in INT_SYNC F1 IN1 in TS4 F2 IN3 in !INT_INHIBIT H1 IN2 in B13C1 H2 IN4 in B14V2 J1 IN3 in !INT_OK J2 OUT out !INT_OK K1 IN4 in !PC_ENABLE K2 IN1 in INT_STROBE L1 OUT out C13L1 L2 IN2 in C14V2 M1 IN1 in !AC08 M2 IN3 in CONTROL_IOT N1 IN2 in !AC09 N2 IN4 in C14V2 P1 IN3 in !AC10 P2 OUT out C13P2 R1 IN4 in !AC11 R2 IN1 in !EA S1 OUT out C13S1 S2 IN2 in !LOCK T1 GND pwr GND T2 IN3 in !LOCK U1 P$1 pas *** unused *** U2 IN4 in MEM_START V1 P$1 pas *** unused *** V2 OUT out C13V2 C14 A1 IN1 in !OP1 A2 VCC pwr VCC B1 IN2 in !OP2 C1 OUT out C14C1 C2 GND pwr GND D1 IN1 in C14C1 D2 IN1 in TP2 E1 IN2 in TP3 E2 IN2 in B_EXECUTE F1 OUT out !OP_STROBE F2 OUT out C14F2 H1 IN1 in PC_LOAD H2 IN1 in A14D1 J1 IN2 in PC_LOAD J2 IN2 in OP2 K1 OUT out !PC_LOAD K2 OUT out C14K2 L1 IN1 in AC00 L2 IN1 in LINK M1 IN2 in MB05 M2 IN2 in MB07 N1 OUT out C14N1 N2 OUT out C14N2 P1 IN1 in KEY_LA+EX+DP P2 IN1 in INT_STROBE R1 IN2 in +3V(13) R2 IN2 in B_FETCH S1 OUT out !KEY_LA+EX+DP S2 OUT out C14S2 T1 GND pwr GND T2 IN1 in !MB10 U1 P$1 pas *** unused *** U2 IN2 in !MB11 V1 P$1 pas *** unused *** V2 OUT out C14V2 C15 A1 IN1 in C13V2 A2 VCC pwr VCC B1 IN2 in C15K2 C1 OUT out C15C1 C2 GND pwr GND D1 IN1 in !MFTS1 D2 IN1 in D14F1 E1 IN2 in !MFTS2 E2 IN2 in CYCLE F1 OUT out C15F1 F2 OUT out C15F2 H1 IN1 in INHIBIT H2 IN1 in LOCK J1 IN2 in D14J1 J2 IN2 in CYC_DONE K1 OUT out C15K1 K2 OUT out C15K2 L1 IN1 in !LOCK L2 IN1 in INT_OK M1 IN2 in CYC_DONE M2 IN2 in TS4 N1 OUT out MEM_DONE_NOT N2 OUT out B36M1 P1 IN1 in DEFER P2 IN1 in !JMS R1 IN2 in !IR0 R2 IN2 in !JMP S1 OUT out B36B1 S2 OUT out B36E2 T1 GND pwr GND T2 IN1 in C05V2 U1 P$1 pas *** unused *** U2 IN2 in MFTP0 V1 P$1 pas *** unused *** V2 OUT out B36J1 C16 A1 IN in MEM_P A2 VCC pwr VCC B1 OUT out !MEM_P C1 IN in MEM00 C2 GND pwr GND D1 IN in MEM01 D2 OUT out !MEM00 E1 OUT out !MEM01 E2 IN in MEM02 F1 IN in MEM03 F2 OUT out !MEM02 H1 OUT out !MEM03 H2 IN in MEM04 J1 IN in MEM05 J2 OUT out !MEM04 K1 OUT out !MEM05 K2 IN in MEM06 L1 IN in MEM07 L2 OUT out !MEM06 M1 OUT out !MEM07 M2 IN in MEM08 N1 IN in MEM09 N2 OUT out !MEM08 P1 OUT out !MEM09 P2 IN in MEM10 R1 IN in MEM11 R2 OUT out !MEM10 S1 OUT out !MEM11 S2 IN in MP_INT T1 GND pwr GND T2 OUT out !MP_INT U1 OUT out *** unused *** U2 IN in *** unused *** V1 IN in *** unused *** V2 OUT out *** unused *** C17 A2 VCC pwr VCC C2 GND pwr GND P2 P in D15J1 R2 R in READ S2 S out STROBE_FIELD0 T2 T oc !STROBE U2 IN in MEM_DONE V2 OUT oc !MEM_DONE C18 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in MA06 F2 F2 in MA08 H2 H2 in MA07 J2 J2 pas C18J2 K2 K2 pas C18K2 L2 L2 pas C18L2 M2 M2 pas C18M2 N2 N2 pas C18N2 P2 P2 pas C18P2 R2 R2 pas C18R2 S2 S2 pas C18S2 T2 T2 in Y_R/W_SOURCE V2 V2 in NEG_CLAMP C19 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in !MA06 F2 F2 in MA08 H2 H2 in MA07 J2 J2 pas C19J2 K2 K2 pas C19K2 L2 L2 pas C19L2 M2 M2 pas C19M2 N2 N2 pas C19N2 P2 P2 pas C19P2 R2 R2 pas C19R2 S2 S2 pas C19S2 T2 T2 in Y_R/W_SOURCE V2 V2 in NEG_CLAMP C20 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io C19K2 D2 P$2 io C19J2 E2 P$2 io C19M2 F2 P$2 io C19L2 H2 P$2 io C19P2 J2 P$2 io C19N2 K2 P$2 io C19S2 L2 P$2 io C19R2 M2 P$2 io C18K2 N2 P$2 io C18J2 P2 P$2 io C18M2 R2 P$2 io C18L2 S2 P$2 io C18P2 T2 P$2 io C18N2 U2 P$2 io C18S2 V2 P$2 io C18R2 C22 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io C24K2 D2 P$2 io C24J2 E2 P$2 io C24M2 F2 P$2 io V24L2 H2 P$2 io C24P2 J2 P$2 io C24N2 K2 P$2 io C24S2 L2 P$2 io C24R2 M2 P$2 io C23K2 N2 P$2 io C23J2 P2 P$2 io C23M2 R2 P$2 io C23L2 S2 P$2 io C23P2 T2 P$2 io C23N2 U2 P$2 io C23S2 V2 P$2 io C23R2 C23 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in MA00 F2 F2 in MA02 H2 H2 in MA01 J2 J2 pas C23J2 K2 K2 pas C23K2 L2 L2 pas C23L2 M2 M2 pas C23M2 N2 N2 pas C23N2 P2 P2 pas C23P2 R2 R2 pas C23R2 S2 S2 pas C23S2 T2 T2 in X_R/W_SOURCE V2 V2 in NEG_CLAMP C24 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in !MA00 F2 F2 in MA02 H2 H2 in MA01 J2 J2 pas C24J2 K2 K2 pas C24K2 L2 L2 pas V24L2 M2 M2 pas C24M2 N2 N2 pas C24N2 P2 P2 pas C24P2 R2 R2 pas C24R2 S2 S2 pas C24S2 T2 T2 in X_R/W_SOURCE V2 V2 in NEG_CLAMP C25 A1 A1 in +3V(13) A2 VCC pwr VCC C2 GND pwr GND D1 D1 in WRITE D2 D2 in READ E1 E1 pas B25F2 E2 E2 in B_MEM_ENABLE F1 H in *** unused *** F2 F2 pas X_R/W_SOURCE H1 J pas *** unused *** H2 H in *** unused *** J1 K pas *** unused *** J2 J pas *** unused *** K1 K1 pas X_R/W_SOURCE K2 K pas *** unused *** L1 L1 in WRITE L2 L2 pas A26F2 M1 M1 pas B26F2 M2 M2 in READ N1 H in *** unused *** N2 N2 in B_MEM_ENABLE P1 J pas *** unused *** P2 P2 pas Y_R/W_SOURCE R1 K pas *** unused *** R2 H in *** unused *** S1 S1 pas Y_R/W_SOURCE S2 J pas *** unused *** T1 GND pwr GND T2 K pas *** unused *** U2 U2 pas A25F2 V2 V2 in NEG_CLAMP C26 A2 VCC pwr VCC C2 GND pwr GND D2 P$1 pas !EA E2 P$1 pas !INT_INHIBIT F2 P$1 pas !WORD_COUNT H2 P$1 pas !CURRENT_ADDR J2 P$1 pas !BREAK K2 P$1 pas *** unused *** L2 P$1 pas *** unused *** M2 P$1 pas *** unused *** N2 P$1 pas *** unused *** P2 P$1 pas BEMA R2 P$1 pas !MP_SKIP S2 P$1 pas !PWR_LOW T2 P$1 pas !WC_SET U2 P$1 pas !RESTART V2 P$1 pas !MP_INT C27 A1 A in MB07 A2 VCC pwr VCC B1 B in !MB08 C1 C in GND C2 GND pwr GND D1 D oc BMB07 D2 A in !RUN E1 E oc !BMB08 E2 B in GND F1 A in MB08 F2 C in GND H1 B in MB09 H2 D oc BRUN J1 C in GND J2 E oc *** unconnected *** K1 D oc BMB08 K2 A in !WC_OVERFLOW L1 E oc BMB09 L2 B in !BREAK M1 A in MB10 M2 C in GND N1 B in MB11 N2 D oc WC_OVERFLOW P1 C in GND P2 E oc !BBREAK R1 D oc BMB10 R2 A in !ADD_ACCEPTED S1 E oc BMB11 S2 B in INITIALIZE T1 GND pwr GND T2 C in GND U1 GND pwr GND U2 D oc !BADD_ACCEPTED V1 GND pwr GND V2 E oc BINITIALIZE2 C28 A1 IN1 in PAUSE A2 VCC pwr VCC B1 IN2 in !TS4 C1 IN3 in !IO_ENABLE C2 GND pwr GND D1 OUT out !IO_PC_ENABLE D2 IN1 in INT_RQST E1 IN1 in *** unused *** E2 IN2 in !KEY_LA+EX+DP F1 IN2 in *** unused *** F2 IN3 in F_SET H1 IN3 in *** unused *** H2 OUT out C28H2 J1 OUT out *** unused *** J2 IN1 in *** unused *** K1 IN1 in *** unused *** K2 IN2 in *** unused *** L1 IN2 in *** unused *** L2 IN3 in *** unused *** M1 IN3 in *** unused *** M2 OUT out *** unused *** N1 OUT out *** unused *** N2 IN1 in *** unused *** P1 IN1 in *** unused *** P2 IN2 in *** unused *** R1 IN2 in *** unused *** R2 IN3 in *** unused *** S1 IN3 in *** unused *** S2 OUT out *** unused *** T1 GND pwr GND T2 IN1 in *** unused *** U1 OUT out *** unused *** U2 IN2 in *** unused *** V1 OUT out *** unused *** V2 IN3 in *** unused *** C29 A2 VCC pwr VCC C2 GND pwr GND D2 OUT out BIOP1 H2 IN1 in !IOP1 J2 IN2 in !IOP1 K2 OUT out BIOP2 N2 IN1 in !IOP2 P2 IN2 in !IOP2 S2 OUT out BIOP4 U2 IN1 in !IOP4 V2 IN2 in !IOP4 C30 A2 VCC pwr VCC C2 GND pwr GND D2 OUT out BTS3 H2 IN1 in !TS3 J2 IN2 in !TS3 K2 OUT out BTS1 N2 IN1 in !TS1 P2 IN2 in !TS1 S2 OUT out BINITIALIZE U2 IN1 in !INITIALIZE V2 IN2 in !INITIALIZE C31 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io *** unused *** D2 P$2 io *** unused *** E1 P$2 io !MB04 E2 P$2 io !MB03 F1 P$2 io MB06 F2 P$2 io !MB05 H1 P$2 io !TTO_ENABLE H2 P$2 io !MB07 J1 P$2 io *** unused *** J2 P$2 io !MB08 K1 P$2 io TTO_ENABLE K2 P$2 io TTO_ENABLE L1 P$2 io !TTO_ENABLE L2 P$2 io AC06 M1 P$2 io *** unused *** M2 P$2 io AC07 N1 P$2 io +3V(15) N2 P$2 io +3V(15) P1 P$2 io *** unused *** P2 P$2 io AC04 R1 P$2 io *** unused *** R2 P$2 io AC05 S1 P$2 io IOP4 S2 P$2 io AC09 T1 P$2 io GND T2 P$2 io AC10 U1 P$2 io AC11 U2 P$2 io AC08 V1 P$2 io *** unused *** V2 P$2 io TXD C32 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io +3V(16) D2 P$2 io !MB03 E1 P$2 io !MB04 E2 P$2 io !KCC F1 P$2 io !MB05 F2 P$2 io !TTI_FLAG H1 P$2 io !MB06 H2 P$2 io MB07 J1 P$2 io MB08 J2 P$2 io TTY8BITS K1 P$2 io TTY8BITS K2 P$2 io !TT0 L1 P$2 io !TT3 L2 P$2 io IOP4 M1 P$2 io !TT4 M2 P$2 io SPIKE_DETECT N1 P$2 io TTI_CLOCK N2 P$2 io !TT7 P1 P$2 io *** unused *** P2 P$2 io !TT5 R1 P$2 io SPIKE_DETECT R2 P$2 io !TT1 S1 P$2 io *** unused *** S2 P$2 io !TT2 T1 P$2 io GND T2 P$2 io !TT6 U1 P$2 io *** unused *** U2 P$2 io READER_RUN V1 P$2 io *** unused *** V2 P$2 io !KCC C33 A2 P$2 io VCC B2 P$2 io *** unused *** C2 P$2 io GND D2 P$2 io *** unused *** E2 P$2 io *** unused *** F2 P$2 io *** unused *** H2 P$2 io *** unused *** J2 P$2 io HZ880 K2 P$2 io !TTO_CLOCK L2 P$2 io *** unused *** M2 P$2 io *** unused *** N2 P$2 io *** unused *** P2 P$2 io HZ880 R2 P$2 io TTI_CLOCK S2 P$2 io *** unused *** T2 P$2 io *** unused *** U2 P$2 io *** unused *** V2 P$2 io *** unused *** C34 A1 P$2 io *** unused *** A2 P$2 io *** unused *** B1 P$2 io *** unused *** B2 P$2 io -15V C1 P$2 io GND C2 P$2 io *** unused *** D1 P$2 io C34D1 D2 P$2 io RD_HOLE1 E1 P$2 io C34E1 E2 P$2 io RD_HOLE2 F1 P$2 io *** unused *** F2 P$2 io RD_HOLE3 H1 P$2 io PB0 H2 P$2 io RD_HOLE4 J1 P$2 io PB1 J2 P$2 io RD_HOLE5 K1 P$2 io PB2 K2 P$2 io RD_HOLE6 L1 P$2 io PB3 L2 P$2 io RD_HOLE7 M1 P$2 io !RDR_DONE M2 P$2 io RD_HOLE8 N1 P$2 io PB4 N2 P$2 io FEED_HOLE P1 P$2 io PB5 P2 P$2 io A R1 P$2 io PB6 R2 P$2 io !A S1 P$2 io PB7 S2 P$2 io !B T1 P$2 io GND T2 P$2 io B U1 P$2 io B31U2 U2 P$2 io PWR V1 P$2 io *** unused *** V2 P$2 io RDR_FEED_SW C35 A1 GND pwr GND B1 P$2 io !BDATA00 C1 GND pwr GND C2 GND pwr GND D1 P$2 io !BDATA01 D2 P$2 io !BDATA09 E1 P$2 io !BDATA02 E2 P$2 io !BDATA10 F1 GND pwr GND F2 GND pwr GND H1 P$2 io !BDATA03 H2 P$2 io !BDATA11 J1 P$2 io !BDATA04 J2 GND pwr GND K1 GND pwr GND K2 P$2 io !3CYCLE L1 P$2 io !BDATA05 L2 GND pwr GND M1 P$2 io !BDATA06 M2 P$2 io CA_INCREMENT N1 GND pwr GND N2 GND pwr GND P1 P$2 io !BDATA07 P2 P$2 io WC_OVERFLOW R1 GND pwr GND R2 GND pwr GND S1 P$2 io !BDATA08 S2 P$2 io !EXT_ADD2 T1 GND pwr GND T2 P$2 io *** unused *** U2 GND pwr GND V2 P$2 io *** unused *** C36 A1 GND pwr GND B1 P$2 io !BADDR00 C1 GND pwr GND C2 GND pwr GND D1 P$2 io !BADDR01 D2 P$2 io !BADDR09 E1 P$2 io !BADDR02 E2 P$2 io !BADDR10 F1 GND pwr GND F2 GND pwr GND H1 P$2 io !BADDR03 H2 P$2 io !BADDR11 J1 P$2 io !BADDR04 J2 GND pwr GND K1 GND pwr GND K2 P$2 io !BRK_RQST L1 P$2 io !BADDR05 L2 GND pwr GND M1 P$2 io !BADDR06 M2 P$2 io DATA_IN N1 GND pwr GND N2 GND pwr GND P1 P$2 io !BADDR07 P2 P$2 io !BBREAK R1 GND pwr GND R2 GND pwr GND S1 P$2 io !BADDR08 S2 P$2 io !BADD_ACCEPTED T1 GND pwr GND T2 P$2 io !BMEM_INCR U2 GND pwr GND V2 P$2 io BINITIALIZE2 CD03 AA2 VCC pwr VCC AC2 GND pwr GND AE2 CE2 out MFTP1 AF2 CF2 out MFTS2 AH2 CH2 out !MFTS2 AJ2 CJ2 out MFTS1 AK2 CK2 out !MFTS1 AL2 CL2 in !POWER_CLEAR AM2 CM2 out MFTS0 AN2 CN2 out *** unconnected *** AP2 CP2 in !RUN AR2 CR2 in !RESTART AS2 CS2 in D01N1 AT2 CT2 out MFTP0 BA2 VCC pwr VCC BC2 GND pwr GND BD2 DD2 out MFTP2 BE2 P$1 pas !STROBE BF2 P$1 pas !MEM_DONE D01 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io PC06 C2 P$2 io GND D1 P$2 io PC07 D2 P$2 io !IR2 E1 P$2 io PC08 E2 P$2 io !DEFER F1 P$2 io PC09 F2 P$2 io !ILLEGAL_REF H1 P$2 io PC10 H2 P$2 io *** unused *** J1 P$2 io PC11 J2 P$2 io !WORD_COUNT K1 P$2 io *** unused *** K2 P$2 io !CURRENT_ADDR L1 P$2 io *** unused *** L2 P$2 io !BREAK M1 P$2 io *** unused *** M2 P$2 io SR11 N1 P$2 io D01N1 N2 P$2 io !KEY_STOP P1 P$2 io !KEY_EX+DP P2 P$2 io !KEY_CONT R1 P$2 io !KEY_ST R2 P$2 io !KEY_ST S1 P$2 io !KEY_CONT S2 P$2 io !KEY_LA T1 P$2 io GND T2 P$2 io !KEY_SS U1 P$2 io !KEY_LA U2 P$2 io !KEY_EX V1 P$2 io D01_10V V2 P$2 io !KEY_DP D02 A1 IN in !KEY_LA A2 VCC pwr VCC B1 OUT out KEY_LA C1 IN in !KEY_DP C2 GND pwr GND D1 IN in KEY_EX+DP D2 OUT out KEY_DP E1 OUT out !KEY_EX+DP E2 IN in !IOP1 F1 IN in !KEY_CONT F2 OUT out IOP1 H1 OUT out KEY_CONT H2 IN in !IOP2 J1 IN in !MFTS3 J2 OUT out IOP2 K1 OUT out MFTS3 K2 IN in !IOP4 L1 IN in !STROBE L2 OUT out IOP4 M1 OUT out TP1 M2 IN in INITIALIZE N1 IN in TP2 N2 OUT out !INITIALIZE P1 OUT out !TP2 P2 IN in !IO_END R1 IN in INT_STROBE R2 OUT out IO_END S1 OUT out !INT_STROBE S2 IN in !WORD_COUNT T1 GND pwr GND T2 OUT out B_WC U1 OUT out KEY_PROTECT U2 IN in !CURRENT_ADDR V1 IN in !KEY_PROTECT V2 OUT out B_CA D04 A1 IN1 in MEM_IDLE A2 VCC pwr VCC B1 IN2 in !PAUSE C1 IN3 in RUN C2 GND pwr GND D1 OUT out D04D1 D2 IN1 in IO_ON E1 IN1 in MFTS0 E2 IN2 in IOP_A F1 IN2 in !MFTS1 F2 IN3 in MB11 H1 IN3 in !MFTS2 H2 OUT out !IOP1 J1 OUT out !MFTS3 J2 IN1 in IO_ON K1 IN1 in !KEY_ST K2 IN2 in IOP_B L1 IN2 in !RESTART L2 IN3 in MB10 M1 IN3 in !KEY_EX+DP M2 OUT out !IOP2 N1 OUT out KEY_ST+EX+DP N2 IN1 in IO_ON P1 IN1 in !MEM_ALT1 P2 IN2 in IOP_C R1 IN2 in !MEM_ALT2 R2 IN3 in MB09 S1 IN3 in !WORD_COUNT S2 OUT out !IOP4 T1 GND pwr GND T2 IN1 in C07L2 U1 OUT out D04U1 U2 IN2 in TS2 V1 OUT out !PROTECT V2 IN3 in D04U1 D05 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D05R2 F1 OUT out D05F1 H1 IN in D06M2 H2 H2 in IO_END J1 OUT out BTP2 J2 J2 out *** unconnected *** K2 K2 out *** unconnected *** L2 L2 out *** unconnected *** M2 M2 out *** unconnected *** N2 N2 out *** unconnected *** P2 P2 out *** unconnected *** R2 R2 out D05R2 S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out *** unconnected *** U2 U2 out *** unconnected *** V2 V2 out *** unconnected *** D06 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D06M2 F1 OUT out TP2 H1 IN in D06T2 H2 H2 in TP1 J1 OUT out TP3 J2 J2 out *** unconnected *** K2 K2 out *** unconnected *** L2 L2 out *** unconnected *** M2 M2 out D06M2 N2 N2 out *** unconnected *** P2 P2 out *** unconnected *** R2 R2 out *** unconnected *** S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out D06T2 U2 U2 out *** unconnected *** V2 V2 out *** unconnected *** D07 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D07N2 F1 OUT out SET_IO_ON H1 IN in D06T2 H2 H2 in C05S1 J1 OUT out BTP3 J2 J2 out *** unconnected *** K2 K2 out D07K2 L2 L2 out *** unconnected *** M2 M2 out *** unconnected *** N2 N2 out D07N2 P2 P2 out *** unconnected *** R2 R2 out *** unconnected *** S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out *** unconnected *** U2 U2 out *** unconnected *** V2 V2 out *** unconnected *** D08 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D08V2 F1 OUT out IO_STROBE H1 IN in D07K2 H2 H2 in SET_IO_ON J1 OUT out !IO_ROT J2 J2 out *** unconnected *** K2 K2 out *** unconnected *** L2 L2 out *** unconnected *** M2 M2 out *** unconnected *** N2 N2 out *** unconnected *** P2 P2 out *** unconnected *** R2 R2 out *** unconnected *** S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out *** unconnected *** U2 U2 out *** unconnected *** V2 V2 out D08V2 D09 A1 IN1A in MB10 A2 VCC pwr VCC B1 IN1B in !MB11 C1 IN1C in OP2 C2 GND pwr GND D1 IN1D in +3V(8) D2 IN1A in +3V(8) E1 IN2A in KEY_STOP E2 IN1B in +3V(8) F1 IN2B in F_SET F2 IN1C in OP2 H1 IN3A in KEY_LA+EX+DP H2 IN1D in !MB04 J1 IN3B in MFTS0 J2 IN2A in IO_ENABLE K1 IN4A in STOP_OK K2 IN2B in !AC_CLEAR L1 IN4B in !POWER_OK L2 IN3A in OP1 M1 IN5A in KEY_SS+I_REF M2 IN3B in D09V2 N1 IN5B in +3V(8) N2 IN4A in !PROTECT P1 IN5C in +3V(8) P2 IN4B in TS2 R1 OUT out D09R1 R2 IN4C in B_EXECUTE S1 IN1A in !MB04 S2 IN4D in DCA T1 GND pwr GND T2 OUT out D09T2 U1 IN1B in MB06 U2 IN2B in !MB06 V1 IN2A in MB04 V2 OUT out D09V2 D10 A1 R in +3V(4) A2 VCC pwr VCC B1 C in TP4 C1 D in !BREAK_OK C2 GND pwr GND D1 S in D11C1 D2 C in TP2 E1 1 out !ADD_ACCEPTED E2 D in D11F2 F1 0 out *** unconnected *** F2 S in !MEM_DONE H1 C in *** unused *** H2 1 out !WC_OVERFLOW J1 D in *** unused *** J2 0 out *** unconnected *** K1 S in *** unused *** K2 R in !MANUAL_PRESET L1 1 out *** unused *** L2 C in TP4 M1 0 out *** unused *** M2 D in D11N2 N1 C in TP4 N2 S in +3V(4) P1 D in WORD_COUNT P2 1 out WORD_COUNT R1 S in +3V(4) R2 0 out !WORD_COUNT S1 1 out *** unconnected *** S2 C in TP4 T1 GND pwr GND T2 D in B_SET U1 0 out !CURRENT_ADDR U2 S in +3V(4) V1 0 out !BREAK V2 1 out BREAK D11 A1 IN1 in +3V(4) A2 VCC pwr VCC B1 IN2 in D11F1 C1 OUT out D11C1 C2 GND pwr GND D1 IN1 in !STROBE D2 IN1 in D11K1 E1 IN2 in !MANUAL_PRESET E2 IN2 in CARRYOUT0 F1 OUT out D11F1 F2 OUT out D11F2 H1 IN1 in !WORD_COUNT H2 IN1 in BREAK J1 IN2 in D11K2 J2 IN2 in MEMORY_INCREMENT K1 OUT out D11K1 K2 OUT out D11K2 L1 IN1 in TS4 L2 IN1 in +3V(4) M1 IN2 in BREAK_OK M2 IN2 in !WC_SET N1 OUT out !DATA_ADD_EN N2 OUT out D11N2 P1 IN1 in !BADDR00 P2 IN1 in !BADDR01 R1 IN2 in !BADDR00 R2 IN2 in !BADDR01 S1 OUT out DATA_ADD00 S2 OUT out DATA_ADD01 T1 GND pwr GND T2 IN1 in !BADDR02 U1 P$1 pas +3V(4) U2 IN2 in !BADDR02 V1 P$1 pas +3V(8) V2 OUT out DATA_ADD02 D12 A1 IN1 in MFTP2 A2 VCC pwr VCC B1 IN2 in KEY_ST C1 OUT out !GO C2 GND pwr GND D1 IN1 in !DEFER D2 IN1 in IR0 E1 IN2 in !JMP E2 IN2 in IR1 F1 OUT out D12F1 F2 OUT out !(IOT+OPR) H1 IN1 in TP2 H2 IN1 in TP4 J1 IN2 in B_FETCH J2 IN2 in INT_OK K1 OUT out D12K1 K2 OUT out D12K2 L1 IN1 in !CURRENT_ADDR L2 IN1 in BREAK_OK M1 IN2 in !WORD_COUNT M2 IN2 in !WC_SET N1 OUT out SPECIAL_CYCLE N2 OUT out D12N2 P1 IN1 in D12N2 P2 IN1 in 3CYCLE R1 IN2 in !CURRENT_ADDR R2 IN2 in BREAK_OK S1 OUT out B_SET S2 OUT out !WC_SET T1 GND pwr GND T2 IN1 in !WC_SET U1 P$1 pas *** unused *** U2 IN2 in !WORD_COUNT V1 P$1 pas *** unused *** V2 OUT out D12V2 D13 A1 IN in !BADDR04 A2 VCC pwr VCC B1 OUT out DATA_ADD04 C1 IN in SPECIAL_CYCLE C2 GND pwr GND D1 IN in !BREAK_OK D2 OUT out !SPECIAL_CYCLE E1 OUT out BREAK_OK E2 IN in !IB00 F1 IN in AC_CLEAR F2 OUT out INPUT_BUS00 H1 OUT out !AC_CLEAR H2 IN in !IB01 J1 IN in !BADDR05 J2 OUT out INPUT_BUS01 K1 OUT out DATA_ADD05 K2 IN in !IB02 L1 IN in TT_INT L2 OUT out INPUT_BUS02 M1 OUT out !TT_INT M2 IN in !IB03 N1 IN in MEM_DONE_NOT N2 OUT out INPUT_BUS03 P1 OUT out MEM_DONE P2 IN in !BADDR06 R1 IN in MEM00 R2 OUT out DATA_ADD06 S1 OUT out D13S1 S2 IN in !BADDR07 T1 GND pwr GND T2 OUT out DATA_ADD07 U1 OUT out !TT_SKIP U2 IN in !BADDR08 V1 IN in TT_SKIP V2 OUT out DATA_ADD08 D14 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D14M2 F1 OUT out D14F1 H1 IN in D14N2 H2 H2 in C15C1 J1 OUT out D14J1 J2 J2 out *** unconnected *** K2 K2 out *** unconnected *** L2 L2 out *** unconnected *** M2 M2 out D14M2 N2 N2 out D14N2 P2 P2 out *** unconnected *** R2 R2 out *** unconnected *** S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out *** unconnected *** U2 U2 out *** unconnected *** V2 V2 out *** unconnected *** D15 A2 VCC pwr VCC C2 GND pwr GND E1 IN in D15T2 F1 OUT out CYC_DONE H1 IN in D15L2 H2 H2 in D14J1 J1 OUT out D15J1 J2 J2 out *** unconnected *** K2 K2 out *** unconnected *** L2 L2 out D15L2 M2 M2 out *** unconnected *** N2 N2 out *** unconnected *** P2 P2 out *** unconnected *** R2 R2 out *** unconnected *** S2 S2 out *** unconnected *** T1 GND pwr GND T2 T2 out D15T2 U2 U2 out *** unconnected *** V2 V2 out *** unconnected *** D16 A1 R in !POWER_CLEAR A2 VCC pwr VCC B1 C in MEM_START C1 D in !EA C2 GND pwr GND D1 S in +3V(13) D2 C in D15J1 E1 1 out *** unconnected *** E2 D in GND F1 0 out !B_MEM_ENABLE F2 S in C15K2 H1 C in CYC_DONE H2 1 out CYCLE J1 D in GND J2 0 out *** unconnected *** K1 S in !MEM_BEGIN K2 R in !POWER_CLEAR L1 1 out READ L2 C in CYC_DONE M1 0 out *** unconnected *** M2 D in GND N1 C in CYC_DONE N2 S in C15F2 P1 D in GND P2 1 out INHIBIT R1 S in C15K1 R2 0 out !INHIBIT S1 1 out WRITE S2 C in WRITE T1 GND pwr GND T2 D in GND U1 0 out *** unconnected *** U2 S in !MEM_BEGIN V1 0 out !LOCK V2 1 out LOCK D17 A1 IN1 in !B_MEM_ENABLE A2 VCC pwr VCC B1 IN2 in !B_MEM_ENABLE C1 IN3 in !B_MEM_ENABLE C2 GND pwr GND D1 IN4 in !B_MEM_ENABLE D2 IN1 in !INHIBIT E1 OUT oc B_MEM_ENABLE E2 IN2 in !INHIBIT F1 IN1 in !B_MEM_ENABLE F2 IN3 in !INHIBIT H1 IN2 in !B_MEM_ENABLE H2 IN4 in !INHIBIT J1 IN3 in !B_MEM_ENABLE J2 OUT oc B_INHIBIT K1 IN4 in !B_MEM_ENABLE K2 IN1 in MFTP1 L1 OUT oc B_MEM_ENABLE L2 IN2 in MFTP1 M1 IN1 in D14J1 M2 IN3 in KEY_LA N1 IN2 in D14J1 N2 IN4 in KEY_LA P1 IN3 in !INHIBIT P2 OUT oc B36H2 R1 IN4 in !INHIBIT R2 IN1 in !F_SET S1 OUT oc !MEM_BEGIN S2 IN2 in !F_SET T1 GND pwr GND T2 IN3 in !E_SET U1 P$1 pas *** unused *** U2 IN4 in !E_SET V1 P$1 pas +3V(13) V2 OUT oc B36D2 D18 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in !MA03 F2 F2 in MA05 H2 H2 in MA04 J2 J2 pas D18J2 K2 K2 pas D18K2 L2 L2 pas D18L2 M2 M2 pas D18M2 N2 N2 pas D18N2 P2 P2 pas D18P2 R2 R2 pas D18R2 S2 S2 pas D18S2 T2 T2 in X_R/W_RETURN V2 V2 in NEG_CLAMP D19 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in MA03 F2 F2 in MA05 H2 H2 in MA04 J2 J2 pas D19J2 K2 K2 pas D19K2 L2 L2 pas D19L2 M2 M2 pas D19M2 N2 N2 pas D19N2 P2 P2 pas D19P2 R2 R2 pas D19R2 S2 S2 pas D19S2 T2 T2 in X_R/W_RETURN V2 V2 in NEG_CLAMP D20 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io D18R2 D2 P$2 io D18S2 E2 P$2 io D18N2 F2 P$2 io D18P2 H2 P$2 io D18L2 J2 P$2 io D18M2 K2 P$2 io D18J2 L2 P$2 io D18K2 M2 P$2 io D19R2 N2 P$2 io D19S2 P2 P$2 io D19N2 R2 P$2 io D19P2 S2 P$2 io D19L2 T2 P$2 io D19M2 U2 P$2 io D19J2 V2 P$2 io D19K2 D22 A2 P$2 io *** unused *** B2 P$2 io *** unused *** C2 P$2 io D23R2 D2 P$2 io D23S2 E2 P$2 io D23N2 F2 P$2 io D23P2 H2 P$2 io D23L2 J2 P$2 io D23M2 K2 P$2 io D23J2 L2 P$2 io D23K2 M2 P$2 io D24R2 N2 P$2 io D24S2 P2 P$2 io D24N2 R2 P$2 io D24P2 S2 P$2 io D24L2 T2 P$2 io D24M2 U2 P$2 io D24J2 V2 P$2 io D24K2 D23 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in !MA09 F2 F2 in MA11 H2 H2 in MA10 J2 J2 pas D23J2 K2 K2 pas D23K2 L2 L2 pas D23L2 M2 M2 pas D23M2 N2 N2 pas D23N2 P2 P2 pas D23P2 R2 R2 pas D23R2 S2 S2 pas D23S2 T2 T2 in Y_R/W_RETURN V2 V2 in NEG_CLAMP D24 A2 VCC pwr VCC C2 GND pwr GND D2 D2 in B_MEM_ENABLE E2 E2 in MA09 F2 F2 in MA11 H2 H2 in MA10 J2 J2 pas D24J2 K2 K2 pas D24K2 L2 L2 pas D24L2 M2 M2 pas D24M2 N2 N2 pas D24N2 P2 P2 pas D24P2 R2 R2 pas D24R2 S2 S2 pas D24S2 T2 T2 in Y_R/W_RETURN V2 V2 in NEG_CLAMP D25 A1 A1 in +3V(13) A2 VCC pwr VCC C2 GND pwr GND D1 D1 in READ D2 D2 in WRITE E1 E1 pas B25F2 E2 E2 in B_MEM_ENABLE F1 H in *** unused *** F2 F2 pas X_R/W_RETURN H1 J pas *** unused *** H2 H in *** unused *** J1 K pas *** unused *** J2 J pas *** unused *** K1 K1 pas X_R/W_RETURN K2 K pas *** unused *** L1 L1 in READ L2 L2 pas A26F2 M1 M1 pas B26F2 M2 M2 in WRITE N1 H in *** unused *** N2 N2 in B_MEM_ENABLE P1 J pas *** unused *** P2 P2 pas Y_R/W_RETURN R1 K pas *** unused *** R2 H in *** unused *** S1 S1 pas Y_R/W_RETURN S2 J pas *** unused *** T1 GND pwr GND T2 K pas *** unused *** U2 U2 pas A25F2 V2 V2 in NEG_CLAMP D27 A1 A in AC00 A2 VCC pwr VCC B1 B in AC01 C1 C in GND C2 GND pwr GND D1 D oc BAC00 D2 A in AC06 E1 E oc BAC01 E2 B in AC07 F1 A in AC02 F2 C in GND H1 B in AC03 H2 D oc BAC06 J1 C in GND J2 E oc BAC07 K1 D oc BAC02 K2 A in AC08 L1 E oc BAC03 L2 B in AC09 M1 A in AC04 M2 C in GND N1 B in AC05 N2 D oc BAC08 P1 C in GND P2 E oc BAC09 R1 D oc BAC04 R2 A in AC10 S1 E oc BAC05 S2 B in AC11 T1 GND pwr GND T2 C in GND U1 GND pwr GND U2 D oc BAC10 V1 GND pwr GND V2 E oc BAC11 D28 A1 A in MB00 A2 VCC pwr VCC B1 B in MB01 C1 C in GND C2 GND pwr GND D1 D oc BMB00 D2 A in MB04 E1 E oc BMB01 E2 B in !MB05 F1 A in MB02 F2 C in GND H1 B in !MB03 H2 D oc BMB04 J1 C in GND J2 E oc !BMB05 K1 D oc BMB02 K2 A in MB05 L1 E oc !BMB03 L2 B in !MB06 M1 A in MB03 M2 C in GND N1 B in !MB04 N2 D oc BMB05 P1 C in GND P2 E oc !BMB06 R1 D oc BMB03 R2 A in MB06 S1 E oc !BMB04 S2 B in !MB07 T1 GND pwr GND T2 C in GND U1 GND pwr GND U2 D oc BMB06 V1 GND pwr GND V2 E oc !BMB07 D29 A1 GND pwr GND A2 VCC pwr VCC B1 P$1 pas BAC00 C1 GND pwr GND C2 GND pwr GND D1 P$1 pas BAC01 D2 P$1 pas BAC09 E1 P$1 pas BAC02 E2 P$1 pas BAC10 F1 GND pwr GND F2 GND pwr GND H1 P$1 pas BAC03 H2 P$1 pas BAC11 J1 P$1 pas BAC04 J2 GND pwr GND K1 GND pwr GND K2 P$1 pas !IB00 L1 P$1 pas BAC05 L2 GND pwr GND M1 P$1 pas BAC06 M2 P$1 pas !IB01 N1 GND pwr GND N2 GND pwr GND P1 P$1 pas BAC07 P2 P$1 pas !IB02 R1 GND pwr GND R2 GND pwr GND S1 P$1 pas BAC08 S2 P$1 pas !IB03 T1 GND pwr GND T2 P$1 pas !BRK_RQST U2 GND pwr GND V2 P$1 pas BRUN D30 A1 GND pwr GND A2 VCC pwr VCC B1 P$1 pas BMB00 C1 GND pwr GND C2 GND pwr GND D1 P$1 pas BMB01 D2 P$1 pas !BMB06 E1 P$1 pas BMB02 E2 P$1 pas BMB06 F1 GND pwr GND F2 GND pwr GND H1 P$1 pas !BMB03 H2 P$1 pas !BMB07 J1 P$1 pas BMB03 J2 GND pwr GND K1 GND pwr GND K2 P$1 pas BMB07 L1 P$1 pas !BMB04 L2 GND pwr GND M1 P$1 pas BMB04 M2 P$1 pas !BMB08 N1 GND pwr GND N2 GND pwr GND P1 P$1 pas !BMB05 P2 P$1 pas BMB08 R1 GND pwr GND R2 GND pwr GND S1 P$1 pas BMB05 S2 P$1 pas BMB09 T1 GND pwr GND T2 P$1 pas BMB10 U2 GND pwr GND V2 P$1 pas BMB11 D31 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io *** unused *** D2 P$2 io IOP2 E1 P$2 io *** unused *** E2 P$2 io INITIALIZE F1 P$2 io *** unused *** F2 P$2 io +3V(15) H1 P$2 io *** unused *** H2 P$2 io IOP1 J1 P$2 io +3V(15) J2 P$2 io !TTO_SKIP K1 P$2 io *** unused *** K2 P$2 io !TTO_FLAG L1 P$2 io *** unused *** L2 P$2 io *** unused *** M1 P$2 io *** unused *** M2 P$2 io *** unused *** N1 P$2 io !OUT_STOP2 N2 P$2 io !OUT_STOP2 P1 P$2 io *** unused *** P2 P$2 io !TTO_CLOCK R1 P$2 io *** unused *** R2 P$2 io *** unused *** S1 P$2 io *** unused *** S2 P$2 io +3V(15) T1 P$2 io GND T2 P$2 io *** unused *** U1 P$2 io *** unused *** U2 P$2 io *** unused *** V1 P$2 io *** unused *** V2 P$2 io *** unused *** D32 A1 P$2 io *** unused *** A2 P$2 io VCC B1 P$2 io *** unused *** B2 P$2 io *** unused *** C1 P$2 io *** unused *** C2 P$2 io GND D1 P$2 io GND D2 P$2 io IOP1 E1 P$2 io *** unused *** E2 P$2 io !TT_AC_CLEAR F1 P$2 io *** unused *** F2 P$2 io INITIALIZE H1 P$2 io *** unused *** H2 P$2 io !TTI_SKIP J1 P$2 io *** unused *** J2 P$2 io IOP2 K1 P$2 io *** unused *** K2 P$2 io *** unused *** L1 P$2 io *** unused *** L2 P$2 io *** unused *** M1 P$2 io *** unused *** M2 P$2 io RXD N1 P$2 io *** unused *** N2 P$2 io *** unused *** P1 P$2 io *** unused *** P2 P$2 io CLOCK_SCALE2 R1 P$2 io +3V(16) R2 P$2 io !IN_STOP2 S1 P$2 io *** unused *** S2 P$2 io *** unused *** T1 P$2 io GND T2 P$2 io CLOCK_SCALE2 U1 P$2 io *** unused *** U2 P$2 io *** unused *** V1 P$2 io *** unused *** V2 P$2 io !IN_STOP2 D33 A2 P$2 io VCC B2 P$2 io -15V C2 P$2 io GND D2 P$2 io *** unused *** E2 P$2 io RXD F2 P$2 io *** unused *** H2 P$2 io TXD J2 P$2 io *** unused *** K2 P$2 io *** unused *** L2 P$2 io *** unused *** M2 P$2 io READER_RUN N2 P$2 io *** unused *** P2 P$2 io *** unused *** R2 P$2 io *** unused *** S2 P$2 io *** unused *** T2 P$2 io *** unused *** U2 P$2 io *** unused *** V2 P$2 io MEM_SUPPLY- D34 A1 GND pwr GND B1 P$2 io !IB00 C1 GND pwr GND C2 GND pwr GND D1 P$2 io !IB01 D2 P$2 io !IB09 E1 P$2 io !IB02 E2 P$2 io !IB10 F1 GND pwr GND F2 GND pwr GND H1 P$2 io !IB03 H2 P$2 io !IB11 J1 P$2 io !IB04 J2 GND pwr GND K1 GND pwr GND K2 P$2 io !BSKIP L1 P$2 io !IB05 L2 GND pwr GND M1 P$2 io !IB06 M2 P$2 io !BIRQ N1 GND pwr GND N2 GND pwr GND P1 P$2 io !IB07 P2 P$2 io !BAC_CLEAR R1 GND pwr GND R2 GND pwr GND S1 P$2 io !IB08 S2 P$2 io BRUN T1 GND pwr GND T2 P$2 io *** unused *** U2 GND pwr GND V2 P$2 io *** unused *** D35 A1 GND pwr GND B1 P$2 io BMB00 C1 GND pwr GND C2 GND pwr GND D1 P$2 io BMB01 D2 P$2 io !BMB06 E1 P$2 io BMB02 E2 P$2 io BMB06 F1 GND pwr GND F2 GND pwr GND H1 P$2 io !BMB03 H2 P$2 io !BMB07 J1 P$2 io BMB03 J2 GND pwr GND K1 GND pwr GND K2 P$2 io BMB07 L1 P$2 io !BMB04 L2 GND pwr GND M1 P$2 io BMB04 M2 P$2 io !BMB08 N1 GND pwr GND N2 GND pwr GND P1 P$2 io !BMB05 P2 P$2 io BMB08 R1 GND pwr GND R2 GND pwr GND S1 P$2 io BMB05 S2 P$2 io BMB09 T1 GND pwr GND T2 P$2 io BMB10 U2 GND pwr GND V2 P$2 io BMB11 D36 A1 GND pwr GND B1 P$2 io BAC00 C1 GND pwr GND C2 GND pwr GND D1 P$2 io BAC01 D2 P$2 io BAC09 E1 P$2 io BAC02 E2 P$2 io BAC10 F1 GND pwr GND F2 GND pwr GND H1 P$2 io BAC03 H2 P$2 io BAC11 J1 P$2 io BAC04 J2 GND pwr GND K1 GND pwr GND K2 P$2 io BIOP1 L1 P$2 io BAC05 L2 GND pwr GND M1 P$2 io BAC06 M2 P$2 io BIOP2 N1 GND pwr GND N2 GND pwr GND P1 P$2 io BAC07 P2 P$2 io BIOP4 R1 GND pwr GND R2 GND pwr GND S1 P$2 io BAC08 S2 P$2 io BTS3 T1 GND pwr GND T2 P$2 io BTS1 U2 GND pwr GND V2 P$2 io BINITIALIZE