+1V2 +3V3 GND +5V DiscFerret Analyser Rev 0J28 TOV TCU BOV BCU (C) 2010 P A Pemberton http://www.discferret.com PCB S/N JTAG BOOT 3V3 MCU FPGA DiscFerret Analyser Rev 0J28 (C) 2010 P A Pemberton http://www.discferret.com +12V 1 1 1 K K + + + K 1 RX TX GND + <b>PQFP20</b> RHL PACKAGE 4.5mm x 3.5mm QFN<p> Source: http://focus.ti.com/lit/ds/symlink/tps75003.pdf Modified to add polarisation marker on tPlace layer >NAME >VALUE <b>SOT-23</b> >NAME >VALUE >NAME >VALUE SwC >NAME >VALUE >NAME >VALUE <b>Small Outline Transistor</b> >NAME >VALUE <b>Small Outline package</b> 150 mil >VALUE >NAME <b>plastic shrink small outline package; 14 leads; body width 5.3 mm</b><p> SOT337-1<br> Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf >NAME >VALUE >NAME >VALUE <b>Footprint Powermite</b> SOD80C, SOD87<p> Source: http://www.semiconductors.philips.com/acrobat_download/literature/9397/75007774.pdf >VALUE >NAME Shielded Tiny Power Inductor WE-TPC >NAME >VALUE SMD-Shielded Power Inductor WE-PD >NAME >VALUE >NAME >VALUE <b>CAPACITOR</b><p> >NAME >VALUE <b>RESISTOR</b> >NAME >VALUE <b>Chip Capacitor </b> Polar tantalum capacitors with solid electrolyte<p> Siemens Matsushita Components B 45 194, B 45 197, B 45 198<br> Source: www.farnell.com/datasheets/247.pdf >NAME >VALUE <b>RESISTOR</b><p> >NAME >VALUE <b>RESISTOR</b> >NAME >VALUE <b>CAPACITOR</b> >NAME >VALUE <b>DIODE</b> >NAME >VALUE <B>DIODE</B><p> diameter 2 mm, horizontal, grid 10.16mm >NAME >VALUE <b>TQFP80</b> 12x12x1 mm Body<p> Source: http://www.microchip.com/ .. 39663c.pdf >NAME >VALUE <b>USB connector</b> with shield<p> >NAME >VALUE E L E C T R O N I C S >NAME <b>TQFP144</b><p> Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 19</i><br> >NAME >VALUE <b>44 PIN TSOP II Z44</b><p> Source: CYPRESS cy7c1049cv33_8.pdf >NAME >VALUE <b>TEST PAD</b> >NAME >VALUE >TP_SIGNAL_NAME <b>CRYSTAL</b> >NAME >VALUE <b>CONNECTOR</b> 1 2 >NAME >VALUE 40 <b>Single In Line</b> >NAME >VALUE 1 <b>PIN HEADER</b> >NAME >VALUE <b>PIN HEADER</b> >NAME >VALUE >name <b>CHIPLED</b><p> Source: http://www.osram.convergy.de/ ... LG_R971.pdf >NAME >VALUE <b>PCB-Pool Multilayer Design Rules</b> <p> Design Rules as specified by PCB-Pool (www.pcb-pool.com) for PCB with 2 or 4 layers. <p> <table border=0 cellpadding=0 cellspacing=0> <tr><td bgcolor="#CCCCCC">Minimum Wire Width</td><td bgcolor="#CCCCCC">0.15mm (6mil)</td></tr> <tr><td>Minimum Wire-to-Wire Clearance</td><td>0.15mm (6mil)</td></tr> <tr><td bgcolor="#CCCCCC">Minimum Drill</td><td bgcolor="#CCCCCC">0.3mm (12mil)</td></tr> <tr><td>Pad/Via Restring ((pad dia - drill dia) / 2)</td><td>0.2mm (8mil)</td></tr> <tr><td bgcolor="#CCCCCC">Solder Stop Vanish Clearance</td><td bgcolor="#CCCCCC">0.15m (6mil)</td></tr> </table>