Project Navigator Auto-Make Log File ------------------------------------- ERROR : Please specify a 'TDO Input File' in the 'TDO Converter' process properties window. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 11 'mydev_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 11 unexpected token: '3' ERROR:HDLCompilers:28 - "rfomni.v" line 11 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 12 'S601_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 12 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 12 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 12 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 12 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 13 'S611_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 13 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 13 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 13 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 13 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 14 'S621_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 14 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 14 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 14 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 14 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 15 'S641_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 15 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 15 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 15 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 15 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 16 'S602_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 16 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 16 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 16 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 16 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 17 'S612_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 17 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 17 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 17 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 17 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 18 'S622_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 18 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 18 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 18 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 18 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 19 'S642_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 19 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 19 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 19 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 19 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 20 'S604_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 20 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 20 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 20 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 20 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 21 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 21 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 21 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 21 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 21 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 22 'S624_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 22 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 22 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 22 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 22 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 23 'S644_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 23 'mydev_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 23 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 23 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 23 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 24 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 24 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 24 'S612_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 24 'S611_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 25 'dsac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 25 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 25 'S612_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 25 'S611_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 26 'diml_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 26 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 26 'S612_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 26 'S611_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 27 'dima_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 27 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 27 'S612_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 27 'S611_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 28 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 28 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 28 'S601_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 29 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 29 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 29 'S601_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 30 'dcim_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 30 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 30 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'S624_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'S614_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'c0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 42 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 42 'bmd_L' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 42 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 42 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 43 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 43 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 44 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 44 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 44 'S612_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 45 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 45 'bmd_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 45 'S642_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 46 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 46 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 47 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 47 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 48 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 49 unexpected token: '9' ERROR:HDLCompilers:28 - "rfomni.v" line 49 'bmd_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 49 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 55 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 56 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 56 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 56 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 56 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 56 expecting ')', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 57 expecting ':', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 66 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 66 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 66 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 66 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 130 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 10 unexpected token: '0' ERROR:HDLCompilers:26 - "rfomni.v" line 10 expecting ':', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 17 unexpected token: '3' ERROR:HDLCompilers:26 - "rfomni.v" line 18 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 19 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 20 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 21 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 22 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 23 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 24 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 25 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 26 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 27 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 28 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 29 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 30 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'dsac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 32 'diml_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 33 'dima_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 48 'c0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '9' WARNING:HDLCompilers:299 - "rfomni.v" line 48 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 49 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 50 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 51 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 52 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 53 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 55 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 55 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 63 expecting ':', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 55 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 17 unexpected token: '3' ERROR:HDLCompilers:26 - "rfomni.v" line 18 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 19 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 20 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 21 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 22 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 23 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 24 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 25 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 26 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 27 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 28 unexpected token: '6' ERROR:HDLCompilers:26 - "rfomni.v" line 29 unexpected token: '6' ERROR:HDLCompilers:28 - "rfomni.v" line 30 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'dsac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 32 'diml_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 33 'dima_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 48 'c0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '9' WARNING:HDLCompilers:299 - "rfomni.v" line 48 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 49 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 50 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 51 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 52 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 53 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 55 unexpected token: '9' ERROR:HDLCompilers:26 - "rfomni.v" line 55 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 63 expecting ':', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 53 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 30 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 31 'dsac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 32 'diml_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 33 'dima_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 34 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'S601_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 35 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_H' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 36 'dcim_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 37 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 42 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 48 'c0_L' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 48 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 48 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 55 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 62 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 32 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 37 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 38 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 39 'tp3' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 40 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 40 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 45 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 45 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 51 'c0_L' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 51 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 51 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 58 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 64 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 74 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 75 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 75 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 75 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 75 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 76 expecting 'end', found '}' ERROR:HDLCompilers:208 - "rfomni.v" line 3 Port reference 'tp3' was not declared as input, inout or output Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 76 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 25 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 41 'skip_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 41 'skp_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 46 'c1_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 46 'dxac_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 52 'c0_L' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 52 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 52 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 59 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 65 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 66 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 75 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 76 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 76 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 76 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 76 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 21 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 48 'dxac_L' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 54 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 17 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" WARNING:HDLCompilers:299 - "rfomni.v" line 54 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 16 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" WARNING:HDLCompilers:299 - "rfomni.v" line 54 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting ';', found '{' ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 78 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 79 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 16 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" WARNING:HDLCompilers:299 - "rfomni.v" line 54 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 54 unexpected token: '1' WARNING:HDLCompilers:299 - "rfomni.v" line 55 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 55 unexpected token: '1' WARNING:HDLCompilers:299 - "rfomni.v" line 56 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 56 unexpected token: 'S612_L' WARNING:HDLCompilers:299 - "rfomni.v" line 57 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 57 unexpected token: 'S642_L' WARNING:HDLCompilers:299 - "rfomni.v" line 58 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: '1' WARNING:HDLCompilers:299 - "rfomni.v" line 59 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 59 unexpected token: '1' WARNING:HDLCompilers:299 - "rfomni.v" line 60 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 60 unexpected token: '1' WARNING:HDLCompilers:299 - "rfomni.v" line 61 Too many digits specified in binary constant ERROR:HDLCompilers:26 - "rfomni.v" line 61 unexpected token: '1' ERROR:HDLCompilers:26 - "rfomni.v" line 61 unexpected token: ';' ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting ':', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 68 expecting ':', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 77 expecting ':', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 78 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 78 expecting ':', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 78 expecting ')', found ',' ERROR:HDLCompilers:26 - "rfomni.v" line 78 expecting ':', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 80 expecting ':', found ')' ERROR:HDLCompilers:26 - "rfomni.v" line 82 expecting ':', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 85 expecting ';', found ')' ERROR:HDLCompilers:26 - "rfomni.v" line 85 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 86 'dar_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 87 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 87 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 8 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 61 expecting ':', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 67 expecting ';', found ')' ERROR:HDLCompilers:26 - "rfomni.v" line 67 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 68 'wc' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 69 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 70 'brk_data_cont_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 67 'dt_l' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 67 'my_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 67 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 68 'wc' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 69 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 70 'brk_data_cont_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 71 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126456 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 69 'dt_l' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 69 'my_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 69 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 70 'wc' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 71 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 72 'brk_data_cont_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 73 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 71 'dt_l' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 71 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 73 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 74 'brk_data_cont_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 75 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 75 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127032 kilobytes Number of errors : 6 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 71 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 73 'ema_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 74 'brk_data_cont_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 75 expecting 'end', found '}' ERROR:HDLCompilers:208 - "rfomni.v" line 2 Port reference 'ema_L' was not declared as input, inout or output Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 75 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 6 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 72 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 74 'ema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 76 expecting 'end', found '}' ERROR:HDLCompilers:208 - "rfomni.v" line 2 Port reference 'ema_L' was not declared as input, inout or output Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 76 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 5 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 9 unexpected token: '0' ERROR:HDLCompilers:26 - "rfomni.v" line 9 expecting ':', found ']' ERROR:HDLCompilers:26 - "rfomni.v" line 83 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 83 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 85 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 85 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 10 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 83 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 83 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dar_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 84 'dma_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 85 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 85 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 85 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 85 unexpected token: '{' ERROR:HDLCompilers:26 - "rfomni.v" line 87 expecting 'end', found '}' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 87 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 4 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 85 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 88 'S501_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 88 'initialize_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 88 unexpected token: '{' ERROR:HDLCompilers:26 - "rfomni.v" line 90 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 90 expecting 'end', found 'else' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 90 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127032 kilobytes Number of errors : 7 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 86 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 89 unexpected token: '{' ERROR:HDLCompilers:26 - "rfomni.v" line 91 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 91 expecting 'end', found 'else' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 91 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126648 kilobytes Number of errors : 5 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 86 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 91 'S542_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 92 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 94 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 96 'S542_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 97 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 100 'S524_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 105 'DXAC_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 106 unexpected token: '.' ERROR:HDLCompilers:26 - "rfomni.v" line 106 expecting ';', found ':' ERROR:HDLCompilers:26 - "rfomni.v" line 106 expecting 'end', found '11' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 107 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 86 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 91 'S542_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 92 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 94 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 96 'S542_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 97 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 100 'S524_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'bwc0_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'overflow_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'wc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 112 'start' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 113 'start_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 113 'start' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 116 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 117 'start_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 118 'busy' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 119 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 119 'error_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 119 unexpected token: ')' ERROR:HDLCompilers:28 - "rfomni.v" line 120 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 125 'done' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 126 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 127 'done' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 131 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 133 'writing' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 134 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 135 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 143 'error_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 143 'error' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 149 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 150 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 152 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 154 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 155 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 159 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 166 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 167 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 168 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 168 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 169 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 169 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126392 kilobytes Number of errors : 60 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 86 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 91 'start_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 92 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 94 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 97 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'bwc0_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'overflow_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 111 'wc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 112 'start' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 113 'start_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 113 'start' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 116 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 117 'start_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 118 'busy' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 119 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 119 'error_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 119 unexpected token: ')' ERROR:HDLCompilers:28 - "rfomni.v" line 120 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 125 'done' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 126 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 127 'done' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 131 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 133 'writing' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 134 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 135 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 138 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 143 'error_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 143 'error' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 149 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 150 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 152 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 154 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 155 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 159 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 166 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 167 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 168 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 168 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 169 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 169 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 87 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 93 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 95 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 98 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 112 'bwc0_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 112 'overflow_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 112 'wc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 117 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 119 'busy' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 120 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 120 'error_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 120 unexpected token: ')' ERROR:HDLCompilers:28 - "rfomni.v" line 121 'busy' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 126 'done' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 127 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 128 'done' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 132 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 134 'writing' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 136 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 139 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 140 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 140 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 140 'writing' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'error_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'error' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 147 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 147 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 147 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 151 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 153 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 156 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 161 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 167 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 168 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 169 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 169 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 170 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 53 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 89 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 95 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 97 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 100 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 114 'bwc0_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 114 'overflow_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 122 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 122 'error_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 122 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 129 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 141 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'error_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'error' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 153 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 155 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 157 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 158 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 162 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 163 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 169 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 170 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 171 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 171 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 172 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 42 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 89 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 97 'dcxa_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 114 'bwc0_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 114 'overflow_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 122 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 122 'error_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 122 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 129 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 141 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 141 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 142 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'error_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 146 'error' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 148 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 149 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 153 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 155 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 157 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 158 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 162 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 163 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 169 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 170 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 171 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 171 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 172 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126840 kilobytes Number of errors : 40 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 92 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 125 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 125 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 132 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 144 'we_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 144 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'setwls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 145 'protect' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 147 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 147 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 151 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 152 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 152 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 152 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 154 'ts4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 154 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 156 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 160 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 161 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 163 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 163 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 165 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 166 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 173 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 174 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 174 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 175 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127032 kilobytes Number of errors : 34 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 97 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 130 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 130 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 152 'ts4_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 156 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 156 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 156 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 159 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 160 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 161 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 163 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 165 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 166 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 168 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 168 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 170 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 171 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 177 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 178 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 179 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 179 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 180 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 180 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 28 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 98 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 131 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 131 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 138 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 157 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'word_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 157 'busy_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'go' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 158 'idle' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 160 'want_db' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 161 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 162 'want_db' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 164 'my_db_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 166 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 167 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 169 'load_cont_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 169 'load_cont' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 171 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 172 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 179 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 180 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 180 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 181 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 181 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126328 kilobytes Number of errors : 27 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 102 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 161 'word_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 165 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 175 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 176 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 182 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 183 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 185 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 185 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 16 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:207 - "rfomni.v" line 16 Signal 'word_L' is not referenced in the module port list ERROR:HDLCompilers:26 - "rfomni.v" line 102 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 161 'word_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 165 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 175 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 176 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 182 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 183 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 185 unexpected token: '=' ERROR:HDLCompilers:208 - "rfomni.v" line 4 Port reference 'word' was not declared as input, inout or output Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 185 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 18 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 102 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 135 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 165 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 175 'break_cycle_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 176 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 182 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 183 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 184 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 185 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 185 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 15 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 103 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 136 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 136 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 151 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 166 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 171 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 177 'ms_disable_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: '{' ERROR:HDLCompilers:28 - "rfomni.v" line 184 'per' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 185 expecting 'end', found '}' ERROR:HDLCompilers:26 - "rfomni.v" line 185 expecting ';', found '{' ERROR:HDLCompilers:26 - "rfomni.v" line 186 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 186 expecting 'endmodule', found '1' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 14 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 104 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 144 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 167 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 186 'setper_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 188 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 192 'int_rq' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'cie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'pie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'eie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'int_rw_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'int_rq' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 196 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 198 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 200 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 205 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 206 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 28 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 104 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 137 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 144 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 167 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 188 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 192 'int_rq' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'cie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'pie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 192 'eie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'int_rw_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'int_rq' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 196 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 198 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 200 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 205 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 206 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 27 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 105 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 138 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 138 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 153 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 168 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 189 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 193 'cie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'pie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 193 'eie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 199 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 200 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 201 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 206 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 206 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 207 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 207 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 49 unexpected token: 'eie' ERROR:HDLCompilers:26 - "rfomni.v" line 49 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 49 expecting 'endmodule', found '3' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 3 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 49 expecting 'endmodule', found ''d' ERROR:HDLCompilers:33 - "rfomni.v" line 49 Illegal digit(s) in decimal constant 'efine' ERROR:HDLCompilers:33 - "rfomni.v" line 50 Illegal digit(s) in decimal constant 'efine' ERROR:HDLCompilers:33 - "rfomni.v" line 51 Illegal digit(s) in decimal constant 'efine' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 4 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 109 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 149 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 157 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 172 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 177 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 193 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 197 'cie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'pie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'eie' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 201 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 204 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 207 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 207 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 210 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 210 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 211 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 211 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 107 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 147 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 191 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 195 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 199 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 201 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 202 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 207 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 207 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 208 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 208 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 209 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 209 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 21 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 107 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 147 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 191 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 195 'cie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 196 'pie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'eie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 198 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 205 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 206 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 208 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 208 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 210 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 210 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 211 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 211 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 212 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 212 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 107 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 140 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 147 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 170 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 191 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 195 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 196 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 197 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 198 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 202 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 204 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 205 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 206 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 208 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 208 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 210 'sr_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 210 'pca_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 211 'sr_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 211 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 212 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 212 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 108 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 156 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 171 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 199 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 207 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 211 'pca_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 212 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 213 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 213 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126648 kilobytes Number of errors : 19 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 108 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 156 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 171 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 199 'pca' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 207 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 212 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 213 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 213 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 18 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 108 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 156 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 171 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 203 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 205 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 207 'wls' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 209 'wls' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 212 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 213 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 213 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 17 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 214 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 215 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 215 expecting 'endmodule', found '2' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 218 expecting ';', found 'begin' ERROR:HDLCompilers:26 - "rfomni.v" line 221 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 221 expecting 'endmodule', found '9' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 222 'per_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 223 'eie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 223 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 224 'pie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 224 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 225 'cie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 225 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 233 'per_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 235 'skp' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 250 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 252 'data' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 267 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 269 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 276 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 281 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 284 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 293 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 295 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 295 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 297 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 298 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 309 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 312 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'bmdeven' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 57 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 223 'eie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 223 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 224 'pie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 224 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 225 'cie_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 225 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 235 'skp' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 250 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 252 'data' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 267 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 269 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 276 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 281 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 284 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 293 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 295 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 295 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 297 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 298 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 309 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 312 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 314 'bmdeven' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 56 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 205 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 232 'skp' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 242 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 247 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 249 'data' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 258 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 264 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 266 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 273 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 275 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 275 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 281 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 287 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 287 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 289 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 294 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 294 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 295 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 295 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 298 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 298 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 299 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 299 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 306 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 309 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'bmdeven' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 50 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 110 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 143 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 150 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 158 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 173 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 205 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 242 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 247 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 249 'data' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 258 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 264 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 266 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 273 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 275 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 275 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 278 'bmdeven' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 281 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 287 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 287 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 289 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 294 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 294 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 295 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 295 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 298 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 298 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 299 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 299 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 306 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 309 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 310 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'bmd' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'odd411' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'bmdeven' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 49 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 111 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 144 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 144 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 151 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 159 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 174 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 179 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 195 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 206 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 243 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 248 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 250 'data' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 259 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 265 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 267 'data' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 274 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 276 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 282 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 288 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 288 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 290 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 291 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 293 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 293 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 295 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 295 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 296 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 296 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 299 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 299 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 300 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 300 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 304 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 304 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 307 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 307 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 311 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 312 'dma_in' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 41 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 112 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 160 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 180 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 196 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 207 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 244 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 260 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 275 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 277 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 283 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 289 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 289 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 291 'dma_in_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 292 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 294 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 294 'dma_out_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 296 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 296 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 297 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 300 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 300 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 301 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 304 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 308 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 312 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'dma_in' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 37 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 112 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 145 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 152 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 160 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 175 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 180 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 196 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 207 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 244 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 260 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 277 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 289 'dma_in' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 294 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 296 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 296 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 297 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 300 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 300 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 301 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 304 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 308 Too many digits specified in binary constant ERROR:HDLCompilers:28 - "rfomni.v" line 312 'pbit' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 313 'dma_in' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 31 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 113 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 153 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 161 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 181 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 197 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 295 'md_dir' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 297 'cs0_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:28 - "rfomni.v" line 298 'cs1_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 309 Too many digits specified in binary constant Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 27 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 113 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 153 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 161 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 181 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 197 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 295 'md_dir' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 309 Too many digits specified in binary constant Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127032 kilobytes Number of errors : 25 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 113 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 153 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 161 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 181 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 197 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 295 'md_dir_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared WARNING:HDLCompilers:299 - "rfomni.v" line 309 Too many digits specified in binary constant ERROR:HDLCompilers:208 - "rfomni.v" line 3 Port reference 'md_dir_L' was not declared as input, inout or output Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 26 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 113 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 146 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 153 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 161 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 176 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 181 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 197 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 208 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 245 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 261 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 297 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 298 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 301 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 302 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 302 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 305 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 306 'dtema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 309 'ema' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126648 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dc_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 304 'dtema_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 304 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 304 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 307 'dtma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'ema' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 23 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 299 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 300 unexpected token: '_L' ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dc_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 304 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 304 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'ema' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126392 kilobytes Number of errors : 20 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 303 'dc_L' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 304 unexpected token: '[' ERROR:HDLCompilers:28 - "rfomni.v" line 304 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'ema' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 18 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 304 'sr' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 308 'ema' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 311 'ema' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 16 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 302 unexpected token: 'posedge' Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126392 kilobytes Number of errors : 13 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 302 expecting 'end', found 'always' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 302 expecting 'endmodule', found '@' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 14 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:27 - "rfomni.v" line 48 Illegal redeclaration of 'per' ERROR:HDLCompilers:26 - "rfomni.v" line 115 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 148 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 155 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 163 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 178 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 183 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 199 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 210 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 247 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 263 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 302 expecting 'end', found 'always' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 302 expecting 'endmodule', found '@' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126840 kilobytes Number of errors : 14 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 114 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 147 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 147 unexpected token: ')' ERROR:HDLCompilers:26 - "rfomni.v" line 154 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 162 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 177 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 182 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 198 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 209 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 246 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 262 unexpected token: 'posedge' ERROR:HDLCompilers:26 - "rfomni.v" line 301 expecting 'end', found 'always' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 301 expecting 'endmodule', found '@' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126456 kilobytes Number of errors : 13 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 114 expecting 'end', found 'always' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 114 expecting 'endmodule', found '@' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126456 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 58 expecting 'endmodule', found 'begin' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 58 expecting 'endmodule', found '~' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126456 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: '<=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 58 expecting 'endmodule', found '~' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: 'mydev_L' ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: '(' ERROR:HDLCompilers:26 - "rfomni.v" line 58 unexpected token: '[' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 58 expecting 'endmodule', found '3' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 4 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 59 unexpected token: '=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 59 expecting 'endmodule', found '~' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 102 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 113 expecting 'end', found 'always' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 113 expecting 'endmodule', found '@' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 111 expecting 'end', found ';' ERROR:HDLCompilers:26 - "rfomni.v" line 114 unexpected token: 'posedge' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 128 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 3 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 114 unexpected token: 'posedge' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 128 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: '<=' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: '|' ERROR:HDLCompilers:26 - "rfomni.v" line 141 unexpected token: ';' ERROR:HDLCompilers:26 - "rfomni.v" line 142 unexpected token: '<=' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 142 expecting 'endmodule', found '!' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 5 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 145 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126136 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 155 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126392 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 167 unexpected token: 'posedge' ERROR:HDLCompilers:28 - "rfomni.v" line 182 'tp4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 183 'tp4' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 188 'tp1' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 189 'tp1' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'load_cont_L' ERROR:HDLCompilers:26 - "rfomni.v" line 192 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'break_cycle_L' ERROR:HDLCompilers:26 - "rfomni.v" line 194 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 195 unexpected token: 'ms_disable_L' ERROR:HDLCompilers:26 - "rfomni.v" line 195 expecting '=', found '?' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 201 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126200 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 188 'tp1' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 189 'tp1' has not been declared ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'load_cont_L' ERROR:HDLCompilers:26 - "rfomni.v" line 192 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'break_cycle_L' ERROR:HDLCompilers:26 - "rfomni.v" line 194 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 195 unexpected token: 'ms_disable_L' ERROR:HDLCompilers:26 - "rfomni.v" line 195 expecting '=', found '?' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 201 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126328 kilobytes Number of errors : 9 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 192 unexpected token: 'load_cont_L' ERROR:HDLCompilers:26 - "rfomni.v" line 192 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 194 unexpected token: 'break_cycle_L' ERROR:HDLCompilers:26 - "rfomni.v" line 194 expecting '=', found '?' ERROR:HDLCompilers:26 - "rfomni.v" line 195 unexpected token: 'ms_disable_L' ERROR:HDLCompilers:26 - "rfomni.v" line 195 expecting '=', found '?' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 201 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126648 kilobytes Number of errors : 7 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 238 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126264 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 301 expecting 'endmodule', found 'if' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 341 expecting 'endmodule', found 'end' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:246 - "rfomni.v" line 245 Reference to scalar reg 'error' is not a legal net lvalue ERROR:HDLCompilers:53 - "rfomni.v" line 245 Illegal left hand side of continuous assign ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 104 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 105 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 106 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 108 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 109 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 110 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127032 kilobytes Number of errors : 60 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 104 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 105 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 106 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 108 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 109 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 110 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126392 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 104 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 110 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 104 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 110 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127224 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 104 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 110 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 104 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 104 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 110 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 132 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 132 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 138 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 138 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 190 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 190 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 242 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 242 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 266 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 266 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 275 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 278 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 283 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 305 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 305 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126840 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 107 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 107 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 110 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 110 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 111 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 111 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 131 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 131 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 133 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 133 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 137 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 137 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 139 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 139 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 191 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 191 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 229 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 229 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 231 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 231 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 241 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 241 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 243 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 243 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 265 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 265 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 267 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 267 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 274 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 276 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 279 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 279 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 284 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 284 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 284 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 286 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 286 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 296 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 296 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 299 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 299 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 304 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 304 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 306 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 306 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 328 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 328 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 330 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 330 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 331 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 331 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127160 kilobytes Number of errors : 58 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 105 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 105 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 109 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 109 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 129 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 129 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 131 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 131 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 135 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 135 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 137 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 137 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 189 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 189 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 227 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 227 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 229 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 229 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 239 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 239 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 241 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 241 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 263 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 263 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 265 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 265 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 272 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 274 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 277 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 277 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 282 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 284 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 284 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 293 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 293 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 296 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 296 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 297 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 297 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 302 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 302 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 304 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 304 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 325 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 325 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 326 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 326 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 328 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 328 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 329 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 329 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 54 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 106 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 106 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 108 Reference to scalar wire 'brk_data_cont_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "rfomni.v" line 108 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 128 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 128 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 130 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 130 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 134 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 134 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 136 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 136 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 188 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 188 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 226 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 226 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 228 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 228 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 238 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 238 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 240 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 240 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 262 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 262 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 264 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 264 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 271 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 276 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 276 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 281 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 281 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 281 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 292 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 292 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 293 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 293 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 296 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 296 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 301 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 301 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 324 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 324 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 325 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 325 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 327 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 327 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 328 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 328 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 50 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 123 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 123 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 125 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 125 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 129 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 129 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 131 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 131 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 183 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 183 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 221 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 221 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 223 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 223 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 233 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 233 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 235 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 235 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 257 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 257 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 259 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 259 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 266 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 271 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 271 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 276 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 276 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 276 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 278 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 278 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 287 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 287 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 290 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 290 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 291 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 291 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 296 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 296 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 298 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 298 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 319 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 319 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 320 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 320 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 322 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 322 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 323 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 323 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 46 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 126 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 126 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 128 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 128 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 180 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 180 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 218 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 218 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 220 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 220 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 230 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 230 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 232 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 232 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 254 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 254 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 256 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 256 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 265 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 273 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 273 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 273 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 275 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 275 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 284 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 284 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 287 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 287 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 293 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 293 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 295 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 295 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 316 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 316 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 317 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 317 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 319 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 319 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 320 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 320 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 42 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 175 Reference to scalar wire 'load_cont' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 175 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 213 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 213 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 215 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 215 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 225 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 225 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 227 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 227 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 249 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 249 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 251 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 251 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 268 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 268 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 270 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 270 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 279 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 279 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 290 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 290 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 311 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 311 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 312 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 312 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 314 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 314 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 315 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 315 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 38 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 213 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 213 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 215 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 215 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 225 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 225 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 227 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 227 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 249 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 249 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 251 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 251 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 268 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 268 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 270 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 270 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 279 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 279 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 290 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 290 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 311 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 311 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 312 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 312 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 314 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 314 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 315 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 315 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 36 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 213 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 213 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 215 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 215 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 225 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 225 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 227 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 227 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 249 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 249 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 251 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 251 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 268 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 268 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 268 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 270 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 270 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 279 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 279 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 290 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 290 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 311 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 311 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 312 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 312 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 314 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 314 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 315 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 315 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 36 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 213 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 213 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 215 Reference to vector wire 'sr_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 215 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 244 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 244 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 246 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 246 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 253 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 255 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 263 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 263 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 263 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 265 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 265 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 274 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 274 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 275 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 275 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 277 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 277 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 278 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 278 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 283 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 283 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 306 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 306 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 307 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 307 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 309 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 309 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 310 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 310 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 32 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 246 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 246 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 248 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 248 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 255 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 257 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 265 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 265 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 265 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 267 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 267 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 276 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 276 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 277 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 277 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 279 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 279 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 287 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 287 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 308 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 308 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 309 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 309 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 311 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 311 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 312 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 312 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 28 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled WARNING:HDLCompilers:192 - "rfomni.v" line 250 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 252 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 255 Most significant bit operand in part-select of vector reg 'dar_L' is out of range WARNING:HDLCompilers:192 - "rfomni.v" line 255 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 260 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 260 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 262 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 262 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 271 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 271 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 272 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 272 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 274 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 274 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 275 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 275 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 304 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 304 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 306 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 306 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 307 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 307 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 260 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 260 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 262 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 262 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 271 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 271 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 272 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 272 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 274 Reference to vector wire 'bmd_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 274 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 275 Reference to scalar wire 'bmdeven' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 275 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 280 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 280 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 282 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 282 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 303 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 303 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 304 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 304 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 306 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 306 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 307 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 307 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 127096 kilobytes Number of errors : 24 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 260 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 260 Illegal left hand side of blocking assignment WARNING:HDLCompilers:192 - "rfomni.v" line 260 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 262 Reference to vector wire 'data_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 262 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 290 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 290 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 291 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 291 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 293 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 293 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 294 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 294 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled WARNING:HDLCompilers:192 - "rfomni.v" line 258 Most significant bit operand in part-select of vector reg 'dar_L' is out of range ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 286 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 286 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 289 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 289 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 285 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 285 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 286 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 286 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 288 Reference to vector wire 'ma_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 288 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 289 Reference to vector wire 'ema_L' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 289 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 108: Unexpected S601_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 132: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 149: Unexpected S604_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 188: Unexpected setper_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 200: Unexpected setwls_L event in always block sensitivity list. WARNING:Xst:905 - "rfomni.v" line 211: The signals are missing in the sensitivity list of always block. ERROR:Xst:902 - "rfomni.v" line 235: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 248: Unexpected S642_L event in always block sensitivity list. ERROR:Xst:871 - "rfomni.v" line 161: Invalid use of input signal as target. WARNING:Xst:864 - "rfomni.v" line 80: Comparisons to 'X' or 'Z' are treated as always false. Found 9 error(s). Aborting synthesis. --> Total memory usage is 126904 kilobytes Number of errors : 9 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 108: Unexpected S601_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 132: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 149: Unexpected S604_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 188: Unexpected setper_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 200: Unexpected setwls_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 235: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 248: Unexpected S642_L event in always block sensitivity list. ERROR:Xst:871 - "rfomni.v" line 161: Invalid use of input signal as target. WARNING:Xst:864 - "rfomni.v" line 80: Comparisons to 'X' or 'Z' are treated as always false. Found 9 error(s). Aborting synthesis. --> Total memory usage is 126392 kilobytes Number of errors : 9 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 108: Unexpected S601_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 132: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 149: Unexpected S604_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 188: Unexpected setper_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 200: Unexpected setwls_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 235: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 248: Unexpected S642_L event in always block sensitivity list. WARNING:Xst:864 - "rfomni.v" line 80: Comparisons to 'X' or 'Z' are treated as always false. Found 8 error(s). Aborting synthesis. --> Total memory usage is 126712 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 108: Unexpected S601_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 132: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 149: Unexpected S604_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 188: Unexpected setper_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 200: Unexpected setwls_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 235: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 248: Unexpected S642_L event in always block sensitivity list. Found 8 error(s). Aborting synthesis. --> Total memory usage is 127096 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 108 unexpected token: ')' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 111 expecting 'endmodule', found 'else' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126840 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 132: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 149: Unexpected S604_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 188: Unexpected setper_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 200: Unexpected setwls_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 235: Unexpected start_L event in always block sensitivity list. ERROR:Xst:902 - "rfomni.v" line 248: Unexpected S642_L event in always block sensitivity list. Found 7 error(s). Aborting synthesis. --> Total memory usage is 126264 kilobytes Number of errors : 7 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:903 - "rfomni.v" line 132: Event in sensitivity list must be a signal or an index. ERROR:Xst:902 - "rfomni.v" line 142: Unexpected S601 event in always block sensitivity list. Found 2 error(s). Aborting synthesis. --> Total memory usage is 126456 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:903 - "rfomni.v" line 132: Event in sensitivity list must be a signal or an index. Found 1 error(s). Aborting synthesis. --> Total memory usage is 126904 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:880 - "rfomni.v" line 139: Cannot mix blocking and non blocking assignments on signal . ERROR:Xst:880 - "rfomni.v" line 135: Cannot mix blocking and non blocking assignments on signal . Found 2 error(s). Aborting synthesis. --> Total memory usage is 126520 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 138 expecting '(', found 'stop' Module compiled ERROR:HDLCompilers:26 - "rfomni.v" line 138 expecting 'endmodule', found 'begin' Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126520 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 212: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1779 - Inout is used but is never assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 128632 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 34 ( 0 filtered) Number of infos : 1 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 212: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:1779 - Inout is used but is never assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 127864 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 33 ( 0 filtered) Number of infos : 1 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 216 expecting ';', found ']' ERROR:HDLCompilers:28 - "rfomni.v" line 218 'data' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126968 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:1779 - Inout is used but is never assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 127672 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 33 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 127736 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 32 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:26 - "rfomni.v" line 81 unexpected token: '2' ERROR:HDLCompilers:26 - "rfomni.v" line 82 unexpected token: '2' Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126648 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 128248 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 28 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . ERROR:Xst:902 - "rfomni.v" line 179: Unexpected initialize_L event in always block sensitivity list. Found 1 error(s). Aborting synthesis. --> Total memory usage is 126264 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. Register
equivalent to has been removed WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 4 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0013 Then 1 If !($n0013) Then - --> Total memory usage is 128696 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 25 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128248 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 26 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128440 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 24 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0049> created at line 314. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 94 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 127992 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 23 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0049> created at line 315. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 94 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128632 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 22 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0050> created at line 315. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 94 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128056 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0050> created at line 316. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 91 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128504 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0050> created at line 315. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 94 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0015 Then 1 If !($n0015) Then - --> Total memory usage is 128120 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0054> created at line 318. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 91 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0055 Then dtema_L[0] If $n0026 Then 1 If $n0027 Then - --> Total memory usage is 128760 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0052> created at line 318. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 94 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Counters : 2 12-bit down counter : 1 8-bit down counter : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 59 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 1 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= ERROR:Xst:528 - Multi-source in Unit on signal Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance CPU : 1.72 / 1.83 s | Elapsed : 2.00 / 2.00 s --> Total memory usage is 130872 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0050> created at line 318. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Counters : 2 12-bit down counter : 1 8-bit down counter : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= ERROR:Xst:528 - Multi-source in Unit on signal Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance CPU : 1.41 / 1.53 s | Elapsed : 2.00 / 2.00 s --> Total memory usage is 131064 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0050> created at line 315. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Counters : 2 12-bit down counter : 1 8-bit down counter : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= ERROR:Xst:528 - Multi-source in Unit on signal Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance ERROR:Xst:528 - Multi-source in Unit on signal > Sources are: Output signal of FDCE instance Output signal of FDCE instance CPU : 1.20 / 1.33 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 131256 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 21 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0046> created at line 290. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Extracting independent architecture files... Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 39 but only 36 left after allocating other resources. ERROR:Cpld:29 - Device XC9536XL-5-PC44 was disqualified. ERROR:Cpld:30 - The design requires too many resources to fit in any of the specified devices. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit 8-to-1 multiplexer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit 4-to-1 multiplexer for signal <$n0008>. Found 8-bit 4-to-1 multiplexer for signal <$n0009>. Found 1-bit xor2 for signal <$n0030> created at line 290. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 46 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 21 Multiplexer(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Multiplexers : 3 1-bit 8-to-1 multiplexer : 1 12-bit 4-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2042 - Unit rf08: 13 internal tristates are replaced by logic (pull-up yes): bmdeven, bmd_L<0>, bmd_L<10>, bmd_L<11>, bmd_L<1>, bmd_L<2>, bmd_L<3>, bmd_L<4>, bmd_L<5>, bmd_L<6>, bmd_L<7>, bmd_L<8>, bmd_L<9>. WARNING:Xst:2040 - Unit rf08: 27 multi-source signals are replaced by logic (pull-up yes): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Loading device for application Rf_Device from file '3s50.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block rf08, actual ratio is 12. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s50pq208-5 Number of Slices: 87 out of 768 11% Number of Slice Flip Flops: 52 out of 1536 3% Number of 4 input LUTs: 127 out of 1536 8% Number of bonded IOBs: 60 out of 124 48% Number of GCLKs: 5 out of 8 62% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ tp3 | BUFGP | 15 | dt:Q | BUFG | 20 | stop(stop1:O) | NONE(*)(busy) | 1 | busy:Q | NONE | 1 | S602(S6021:O) | NONE(*)(writing) | 1 | tp4 | BUFGP | 1 | my_db:Q | BUFG | 4 | tp1 | BUFGP | 1 | S601(S6011:O) | NONE(*)(wls) | 2 | diml_L(diml_L1:O) | NONE(*)(f_L_0) | 6 | -----------------------------------+------------------------+-------+ (*) These 4 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Timing Summary: --------------- Speed Grade: -5 Minimum period: 5.724ns (Maximum Frequency: 174.694MHz) Minimum input arrival time before clock: 8.139ns Maximum output required time after clock: 17.379ns Maximum combinational path delay: 17.076ns ========================================================================= Started process "Translate". Command Line: ngdbuild -intstyle ise -dd c:\users\vince\documents\websvn\trunk\pdp8\rfomni/_ngo -i -p xc3s50-pq208-5 rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Map". Using target part "3s50pq208-5". Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 9 Logic Utilization: Number of Slice Flip Flops: 34 out of 1,536 2% Number of 4 input LUTs: 145 out of 1,536 9% Logic Distribution: Number of occupied Slices: 83 out of 768 10% Number of Slices containing only related logic: 83 out of 83 100% Number of Slices containing unrelated logic: 0 out of 83 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 146 out of 1,536 9% Number used as logic: 145 Number used as a route-thru: 1 Number of bonded IOBs: 60 out of 124 48% IOB Flip Flops: 12 IOB Latches: 6 Number of GCLKs: 5 out of 8 62% Total equivalent gate count for design: 1,496 Additional JTAG gate count for IOBs: 2,880 Peak Memory Usage: 157 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "rf08_map.mrp" for details. Started process "Place & Route". Constraints file: rf08.pcf. Loading device for application Rf_Device from file '3s50.nph' in environment C:/Xilinx. "rf08" is an NCD, version 3.1, device xc3s50, package pq208, speed -5 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "ADVANCED 1.35 2005-01-22". Device Utilization Summary: Number of BUFGMUXs 5 out of 8 62% Number of External IOBs 60 out of 124 48% Number of LOCed IOBs 0 out of 60 0% Number of Slices 83 out of 768 10% Number of SLICEMs 0 out of 384 0% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Starting Placer Phase 1.1 Phase 1.1 (Checksum:9898ab) REAL time: 1 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs Phase 3.2 . Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs Phase 4.3 Phase 4.3 (Checksum:26259fc) REAL time: 1 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs Phase 6.8 . Phase 6.8 (Checksum:9bbb93) REAL time: 1 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs Phase 8.18 Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs Writing design to file rf08.ncd Total REAL time to Placer completion: 1 secs Total CPU time to Placer completion: 0 secs Starting Router Phase 1: 652 unrouted; REAL time: 1 secs Phase 2: 606 unrouted; REAL time: 1 secs Phase 3: 271 unrouted; REAL time: 1 secs Phase 4: 0 unrouted; REAL time: 1 secs WARNING:CLK Net:tp4_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:tp1_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:stop may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:CLK Net:S602 may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:CLK Net:S601 may have excessive skew because 2 CLK pins and 2 NON_CLK pins failed to route using a CLK template. WARNING:CLK Net:busy may have excessive skew because 1 CLK pins and 5 NON_CLK pins failed to route using a CLK template. WARNING:CLK Net:my_db may have excessive skew because 18 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:tp3_BUFGP may have excessive skew because 18 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:dt may have excessive skew because 62 NON-CLK pins failed to route using a CLK template. Total REAL time to Router completion: 1 secs Total CPU time to Router completion: 0 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | my_db | BUFGMUX3| No | 22 | 0.002 | 0.541 | +---------------------+--------------+------+------+------------+-------------+ | tp3_BUFGP | BUFGMUX5| No | 32 | 0.106 | 0.656 | +---------------------+--------------+------+------+------------+-------------+ | tp4_BUFGP | BUFGMUX7| No | 2 | 0.000 | 0.558 | +---------------------+--------------+------+------+------------+-------------+ | tp1_BUFGP | BUFGMUX2| No | 2 | 0.000 | 0.604 | +---------------------+--------------+------+------+------------+-------------+ | dt | BUFGMUX0| No | 74 | 0.058 | 0.599 | +---------------------+--------------+------+------+------------+-------------+ | diml_L | Local| | 6 | 0.142 | 2.471 | +---------------------+--------------+------+------+------------+-------------+ | busy | Local| | 6 | 0.000 | 1.296 | +---------------------+--------------+------+------+------------+-------------+ | stop | Local| | 2 | 0.000 | 0.321 | +---------------------+--------------+------+------+------------+-------------+ | S601 | Local| | 4 | 0.601 | 1.534 | +---------------------+--------------+------+------+------------+-------------+ | S602 | Local| | 2 | 0.000 | 1.209 | +---------------------+--------------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 104 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file rf08.ncd PAR done! Started process "Generate Post-Place & Route Static Timing". Loading device for application Rf_Device from file '3s50.nph' in environment C:/Xilinx. "rf08" is an NCD, version 3.1, device xc3s50, package pq208, speed -5 Analysis completed Fri Apr 18 08:23:46 2014 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 1 secs Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". WARNING:PhysDesignRules:372 - Gated clock. Clock net diml_L is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net stop is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net S601 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net S602 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0046> created at line 290. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC9572XL-5-PC44. ERROR:Cpld:848 - Insufficient number of output pins. This design needs at least 27 but only 22 left after allocating other resources. ERROR:Cpld:29 - Device XC9572XL-5-PC44 was disqualified. ERROR:Cpld:30 - The design requires too many resources to fit in any of the specified devices. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0046> created at line 290. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 100 equations into 8 function blocks........................................................................................................................................................................................................................................................................................................................................................ Design rf08 has been optimized and fit into device XC95144XL-5-TQ100. Started process "Generate Programming File". Release 7.1i - Programming File Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1610. ........ The number of paths traced: 3221. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Set property "resynthesize = true" for unit . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0046> created at line 288. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 100 equations into 8 function blocks........................................................................................................................................................................................................................................................................................................................................................ Design rf08 has been optimized and fit into device XC95144XL-5-TQ100. Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1610. ........ The number of paths traced: 3221. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 226 'f' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:108 - "rfomni.v" line 226 Part-select of scalar wire 'sr' is illegal ERROR:HDLCompilers:53 - "rfomni.v" line 226 Illegal left hand side of continuous assign ERROR:HDLCompilers:247 - "rfomni.v" line 216 Reference to scalar wire 'eie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 216 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 217 Reference to scalar wire 'pie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 217 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 218 Reference to scalar wire 'cie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 218 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 221 Reference to scalar wire 'eie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 221 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 222 Reference to scalar wire 'pie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 222 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 223 Reference to scalar wire 'cie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 223 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126712 kilobytes Number of errors : 14 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled ERROR:HDLCompilers:247 - "rfomni.v" line 216 Reference to scalar wire 'eie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 216 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 217 Reference to scalar wire 'pie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 217 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 218 Reference to scalar wire 'cie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 218 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 221 Reference to scalar wire 'eie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 221 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 222 Reference to scalar wire 'pie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 222 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "rfomni.v" line 223 Reference to scalar wire 'cie' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "rfomni.v" line 223 Illegal left hand side of blocking assignment Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126584 kilobytes Number of errors : 12 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 214: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. Set property "resynthesize = true" for unit . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0059> created at line 287. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit subtractor : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 100 equations into 8 function blocks.......................................................................................................................................................................................................................................................................................................................................................... Design rf08 has been optimized and fit into device XC95144XL-5-TQ100. Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1612. ........ The number of paths traced: 3225. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 238 'dar' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 238 'dma' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 238 'dar' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 238 'dma' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 241 'dma' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 243 'dma' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 246 'dar' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 248 'dar' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126904 kilobytes Number of errors : 8 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" ERROR:HDLCompilers:28 - "rfomni.v" line 253 'dma_L' has not been declared ERROR:HDLCompilers:28 - "rfomni.v" line 254 'dar_L' has not been declared Module compiled Analysis of file <"rf08.prj"> failed. --> Total memory usage is 126776 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 214: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. Set property "resynthesize = true" for unit . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit register for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 20-bit adder for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0078> created at line 284. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 8 function blocks....................................................................................................................................................................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal f<0>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. ..................... ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 16 function blocks......................................................................................................................................... Design rf08 has been optimized and fit into device XC95288XL-6-TQ144. Started process "Generate Programming File". Release 7.1i - Programming File Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 214: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit register for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 20-bit adder for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0078> created at line 284. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 16 function blocks......................................................................................................................................... Design rf08 has been optimized and fit into device XC95288XL-6-TQ144. Started process "Generate Programming File". Release 7.1i - Programming File Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1730. ......... The number of paths traced: 3461. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 214: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit register for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 20-bit adder for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0078> created at line 284. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 16 function blocks......................................................................................................................................... Design rf08 has been optimized and fit into device XC95288XL-6-TQ144. Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1730. ......... The number of paths traced: 3461. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Set property "resynthesize = true" for unit . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit register for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 20-bit adder for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0078> created at line 284. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 16 function blocks......................................................................................................................................... Design rf08 has been optimized and fit into device XC95288XL-6-TQ144. Started process "Generate Timing". Release 7.1i - Timing Report Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_tp1:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. Path tracing ............. The number of paths traced: 1730. ......... The number of paths traced: 3461. Checking for asynchronous logic... Generating TA GUI report ... Generating detailed paths report ... c:\users\vince\documents\websvn\trunk\pdp8\rfomni/rf08_html/tim/timing_report.ht m has been created. Started process "Generate HTML report". Release 7.1i - CPLD HTML Report Processor H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register
seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 3-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit register for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 20-bit adder for signal <$AUX_1>. Found 1-bit xor2 for signal <$n0078> created at line 284. Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal
. Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor12 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Xor(s). inferred 97 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 20-bit adder : 1 # Registers : 15 1-bit register : 11 12-bit register : 2 3-bit register : 1 8-bit register : 1 # Latches : 4 1-bit latch : 3 3-bit latch : 1 # Tristates : 60 1-bit tristate buffer : 55 12-bit tristate buffer : 3 3-bit tristate buffer : 2 # Xors : 2 1-bit xor12 : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2183 - Unit rf08: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N35, N37, N39, N41, N43, N45, N47, N49, N5, N51, N53, N55, N7, N9. Optimizing unit ... Started process "Translate". Release 7.1i - ngdbuild H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl rf08.ngc rf08.ngd Reading NGO file 'C:/Users/Vince/Documents/websvn/trunk/pdp8/rfomni/rf08.ngc' ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "rf08.ngd" ... Writing NGDBUILD log file "rf08.bld"... NGDBUILD done. Started process "Fit". Release 7.1i - CPLD Optimizer/Partitioner H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................................................................................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 101 equations into 16 function blocks......................................................................................................................................... Design rf08 has been optimized and fit into device XC95288XL-6-TQ144. Started process "Generate Programming File". Release 7.1i - Programming File Generator H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "View HDL Instantiation Template". Compiling verilog file "rfomni.v" tdtfi(verilog) completed successfully. Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling verilog file "rfomni.v" tdtfi(verilog) completed successfully.