-------------------------------------------------------------------------------- Release 7.1i Trace H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. C:/Xilinx/bin/nt/trce.exe -ise c:\users\vince\documents\websvn\trunk\pdp8\rfomni\rfomni.ise -intstyle ise -e 3 -l 3 -s 5 -xml rf08 rf08.ncd -o rf08.twr rf08.pcf Design file: rf08.ncd Physical constraint file: rf08.pcf Device,speed: xc3s50,-5 (ADVANCED 1.35 2005-01-22) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock md_L<10> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -0.228(R)| 3.018(R)|diml_L | 0.000| data_L<4> | -0.227(R)| 3.017(R)|diml_L | 0.000| data_L<5> | -0.210(R)| 2.996(R)|diml_L | 0.000| data_L<6> | -0.114(R)| 2.876(R)|diml_L | 0.000| data_L<7> | -0.117(R)| 2.879(R)|diml_L | 0.000| data_L<8> | -0.114(R)| 2.876(R)|diml_L | 0.000| initialize | -0.460(R)| 2.737(R)|S602 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<11> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -0.128(R)| 2.893(R)|diml_L | 0.000| data_L<4> | -0.127(R)| 2.892(R)|diml_L | 0.000| data_L<5> | -0.110(R)| 2.871(R)|diml_L | 0.000| data_L<6> | -0.014(R)| 2.751(R)|diml_L | 0.000| data_L<7> | -0.017(R)| 2.754(R)|diml_L | 0.000| data_L<8> | -0.014(R)| 2.751(R)|diml_L | 0.000| initialize | 0.480(R)| 2.100(R)|S601 | 0.000| protect | -0.325(R)| 2.744(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<3> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -2.465(R)| 5.816(R)|diml_L | 0.000| data_L<4> | -2.464(R)| 5.815(R)|diml_L | 0.000| data_L<5> | -2.447(R)| 5.794(R)|diml_L | 0.000| data_L<6> | -2.351(R)| 5.674(R)|diml_L | 0.000| data_L<7> | -2.354(R)| 5.677(R)|diml_L | 0.000| data_L<8> | -2.351(R)| 5.674(R)|diml_L | 0.000| initialize | -0.881(R)| 3.801(R)|S601 | 0.000| | -1.850(R)| 4.476(R)|S602 | 0.000| protect | -1.686(R)| 4.445(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<4> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -2.638(R)| 6.032(R)|diml_L | 0.000| data_L<4> | -2.637(R)| 6.031(R)|diml_L | 0.000| data_L<5> | -2.620(R)| 6.010(R)|diml_L | 0.000| data_L<6> | -2.524(R)| 5.890(R)|diml_L | 0.000| data_L<7> | -2.527(R)| 5.893(R)|diml_L | 0.000| data_L<8> | -2.524(R)| 5.890(R)|diml_L | 0.000| initialize | -0.913(R)| 3.841(R)|S601 | 0.000| | -1.882(R)| 4.516(R)|S602 | 0.000| protect | -1.718(R)| 4.485(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<5> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -2.766(R)| 6.192(R)|diml_L | 0.000| data_L<4> | -2.765(R)| 6.191(R)|diml_L | 0.000| data_L<5> | -2.748(R)| 6.170(R)|diml_L | 0.000| data_L<6> | -2.652(R)| 6.050(R)|diml_L | 0.000| data_L<7> | -2.655(R)| 6.053(R)|diml_L | 0.000| data_L<8> | -2.652(R)| 6.050(R)|diml_L | 0.000| initialize | -0.410(R)| 3.213(R)|S601 | 0.000| | -1.379(R)| 3.888(R)|S602 | 0.000| protect | -1.215(R)| 3.857(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<6> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -1.430(R)| 4.522(R)|diml_L | 0.000| data_L<4> | -1.429(R)| 4.521(R)|diml_L | 0.000| data_L<5> | -1.412(R)| 4.500(R)|diml_L | 0.000| data_L<6> | -1.316(R)| 4.380(R)|diml_L | 0.000| data_L<7> | -1.319(R)| 4.383(R)|diml_L | 0.000| data_L<8> | -1.316(R)| 4.380(R)|diml_L | 0.000| initialize | -0.343(R)| 3.128(R)|S601 | 0.000| | -1.312(R)| 3.803(R)|S602 | 0.000| protect | -1.148(R)| 3.772(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<7> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -2.271(R)| 5.573(R)|diml_L | 0.000| data_L<4> | -2.270(R)| 5.572(R)|diml_L | 0.000| data_L<5> | -2.253(R)| 5.551(R)|diml_L | 0.000| data_L<6> | -2.157(R)| 5.431(R)|diml_L | 0.000| data_L<7> | -2.160(R)| 5.434(R)|diml_L | 0.000| data_L<8> | -2.157(R)| 5.431(R)|diml_L | 0.000| initialize | 0.844(R)| 1.644(R)|S601 | 0.000| | -0.125(R)| 2.319(R)|S602 | 0.000| protect | 0.039(R)| 2.288(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<8> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -1.138(R)| 4.156(R)|diml_L | 0.000| data_L<4> | -1.137(R)| 4.155(R)|diml_L | 0.000| data_L<5> | -1.120(R)| 4.134(R)|diml_L | 0.000| data_L<6> | -1.024(R)| 4.014(R)|diml_L | 0.000| data_L<7> | -1.027(R)| 4.017(R)|diml_L | 0.000| data_L<8> | -1.024(R)| 4.014(R)|diml_L | 0.000| initialize | -0.512(R)| 3.339(R)|S601 | 0.000| | -1.481(R)| 4.014(R)|S602 | 0.000| protect | -1.317(R)| 3.983(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock md_L<9> ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<3> | -1.262(R)| 4.311(R)|diml_L | 0.000| data_L<4> | -1.261(R)| 4.310(R)|diml_L | 0.000| data_L<5> | -1.244(R)| 4.289(R)|diml_L | 0.000| data_L<6> | -1.148(R)| 4.169(R)|diml_L | 0.000| data_L<7> | -1.151(R)| 4.172(R)|diml_L | 0.000| data_L<8> | -1.148(R)| 4.169(R)|diml_L | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock overflow_L ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ initialize | 1.296(R)| 0.665(R)|stop | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock tp3 ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ initialize | 0.198(R)| 2.319(R)|S601 | 0.000| | -0.510(R)| 2.683(R)|S602 | 0.000| md_L<0> | 2.959(R)| -1.006(R)|tp3_BUFGP | 0.000| md_L<1> | 2.963(R)| -1.011(R)|tp3_BUFGP | 0.000| md_L<2> | 3.036(R)| -1.098(R)|tp3_BUFGP | 0.000| protect | -0.607(R)| 2.963(R)|S601 | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock tp4 ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ data_L<0> | 1.691(R)| -0.399(R)|tp4_BUFGP | 0.000| data_L<1> | 1.765(R)| -0.457(R)|tp4_BUFGP | 0.000| data_L<2> | 1.681(R)| -0.391(R)|tp4_BUFGP | 0.000| data_L<3> | 1.228(R)| -0.029(R)|tp4_BUFGP | 0.000| data_L<4> | 1.479(R)| -0.230(R)|tp4_BUFGP | 0.000| data_L<5> | 1.559(R)| -0.293(R)|tp4_BUFGP | 0.000| data_L<6> | 3.927(R)| -2.187(R)|tp4_BUFGP | 0.000| word_L | 3.560(R)| -1.893(R)|tp4_BUFGP | 0.000| ------------+------------+------------+------------------+--------+ Clock md_L<10> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 12.530(R)|S602 | 0.000| c1_L | 14.884(R)|S602 | 0.000| data_L<0> | 17.982(R)|S602 | 0.000| data_L<10> | 18.089(R)|S602 | 0.000| data_L<11> | 18.514(R)|S602 | 0.000| data_L<1> | 17.986(R)|S602 | 0.000| data_L<2> | 18.773(R)|S602 | 0.000| data_L<3> | 18.318(R)|S602 | 0.000| | 14.847(R)|diml_L | 0.000| data_L<4> | 20.398(R)|S602 | 0.000| | 15.495(R)|diml_L | 0.000| data_L<5> | 19.769(R)|S602 | 0.000| | 14.314(R)|diml_L | 0.000| data_L<6> | 19.569(R)|S602 | 0.000| | 14.758(R)|diml_L | 0.000| data_L<7> | 18.498(R)|S602 | 0.000| | 13.701(R)|diml_L | 0.000| data_L<8> | 18.139(R)|S602 | 0.000| | 13.869(R)|diml_L | 0.000| data_L<9> | 18.298(R)|S602 | 0.000| int_rq_L | 15.260(R)|diml_L | 0.000| md_dir_L | 13.435(R)|S602 | 0.000| skip_L | 13.573(R)|S602 | 0.000| we_L | 11.674(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<11> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ data_L<11> | 14.954(R)|S601 | 0.000| data_L<2> | 14.314(R)|S601 | 0.000| data_L<3> | 14.722(R)|diml_L | 0.000| data_L<4> | 15.370(R)|diml_L | 0.000| data_L<5> | 14.189(R)|diml_L | 0.000| data_L<6> | 14.633(R)|diml_L | 0.000| data_L<7> | 13.576(R)|diml_L | 0.000| data_L<8> | 13.744(R)|diml_L | 0.000| int_rq_L | 13.089(R)|S601 | 0.000| | 15.135(R)|diml_L | 0.000| ------------+------------+------------------+--------+ Clock md_L<3> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 14.269(R)|S602 | 0.000| c1_L | 16.623(R)|S602 | 0.000| data_L<0> | 19.721(R)|S602 | 0.000| data_L<10> | 19.828(R)|S602 | 0.000| data_L<11> | 16.655(R)|S601 | 0.000| | 20.253(R)|S602 | 0.000| data_L<1> | 19.725(R)|S602 | 0.000| data_L<2> | 16.015(R)|S601 | 0.000| | 20.512(R)|S602 | 0.000| data_L<3> | 20.057(R)|S602 | 0.000| | 17.645(R)|diml_L | 0.000| data_L<4> | 22.137(R)|S602 | 0.000| | 18.293(R)|diml_L | 0.000| data_L<5> | 21.508(R)|S602 | 0.000| | 17.112(R)|diml_L | 0.000| data_L<6> | 21.308(R)|S602 | 0.000| | 17.556(R)|diml_L | 0.000| data_L<7> | 20.237(R)|S602 | 0.000| | 16.499(R)|diml_L | 0.000| data_L<8> | 19.878(R)|S602 | 0.000| | 16.667(R)|diml_L | 0.000| data_L<9> | 20.037(R)|S602 | 0.000| int_rq_L | 14.790(R)|S601 | 0.000| | 18.058(R)|diml_L | 0.000| md_dir_L | 15.174(R)|S602 | 0.000| skip_L | 15.312(R)|S602 | 0.000| we_L | 13.413(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<4> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 14.309(R)|S602 | 0.000| c1_L | 16.663(R)|S602 | 0.000| data_L<0> | 19.761(R)|S602 | 0.000| data_L<10> | 19.868(R)|S602 | 0.000| data_L<11> | 16.695(R)|S601 | 0.000| | 20.293(R)|S602 | 0.000| data_L<1> | 19.765(R)|S602 | 0.000| data_L<2> | 16.055(R)|S601 | 0.000| | 20.552(R)|S602 | 0.000| data_L<3> | 20.097(R)|S602 | 0.000| | 17.861(R)|diml_L | 0.000| data_L<4> | 22.177(R)|S602 | 0.000| | 18.509(R)|diml_L | 0.000| data_L<5> | 21.548(R)|S602 | 0.000| | 17.328(R)|diml_L | 0.000| data_L<6> | 21.348(R)|S602 | 0.000| | 17.772(R)|diml_L | 0.000| data_L<7> | 20.277(R)|S602 | 0.000| | 16.715(R)|diml_L | 0.000| data_L<8> | 19.918(R)|S602 | 0.000| | 16.883(R)|diml_L | 0.000| data_L<9> | 20.077(R)|S602 | 0.000| int_rq_L | 14.830(R)|S601 | 0.000| | 18.274(R)|diml_L | 0.000| md_dir_L | 15.214(R)|S602 | 0.000| skip_L | 15.352(R)|S602 | 0.000| we_L | 13.453(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<5> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 13.681(R)|S602 | 0.000| c1_L | 16.035(R)|S602 | 0.000| data_L<0> | 19.133(R)|S602 | 0.000| data_L<10> | 19.240(R)|S602 | 0.000| data_L<11> | 16.067(R)|S601 | 0.000| | 19.665(R)|S602 | 0.000| data_L<1> | 19.137(R)|S602 | 0.000| data_L<2> | 15.427(R)|S601 | 0.000| | 19.924(R)|S602 | 0.000| data_L<3> | 19.469(R)|S602 | 0.000| | 18.021(R)|diml_L | 0.000| data_L<4> | 21.549(R)|S602 | 0.000| | 18.669(R)|diml_L | 0.000| data_L<5> | 20.920(R)|S602 | 0.000| | 17.488(R)|diml_L | 0.000| data_L<6> | 20.720(R)|S602 | 0.000| | 17.932(R)|diml_L | 0.000| data_L<7> | 19.649(R)|S602 | 0.000| | 16.875(R)|diml_L | 0.000| data_L<8> | 19.290(R)|S602 | 0.000| | 17.043(R)|diml_L | 0.000| data_L<9> | 19.449(R)|S602 | 0.000| int_rq_L | 14.202(R)|S601 | 0.000| | 18.434(R)|diml_L | 0.000| md_dir_L | 14.586(R)|S602 | 0.000| skip_L | 14.724(R)|S602 | 0.000| we_L | 12.825(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<6> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 13.596(R)|S602 | 0.000| c1_L | 15.950(R)|S602 | 0.000| data_L<0> | 19.048(R)|S602 | 0.000| data_L<10> | 19.155(R)|S602 | 0.000| data_L<11> | 15.982(R)|S601 | 0.000| | 19.580(R)|S602 | 0.000| data_L<1> | 19.052(R)|S602 | 0.000| data_L<2> | 15.342(R)|S601 | 0.000| | 19.839(R)|S602 | 0.000| data_L<3> | 19.384(R)|S602 | 0.000| | 16.351(R)|diml_L | 0.000| data_L<4> | 21.464(R)|S602 | 0.000| | 16.999(R)|diml_L | 0.000| data_L<5> | 20.835(R)|S602 | 0.000| | 15.818(R)|diml_L | 0.000| data_L<6> | 20.635(R)|S602 | 0.000| | 16.262(R)|diml_L | 0.000| data_L<7> | 19.564(R)|S602 | 0.000| | 15.205(R)|diml_L | 0.000| data_L<8> | 19.205(R)|S602 | 0.000| | 15.373(R)|diml_L | 0.000| data_L<9> | 19.364(R)|S602 | 0.000| int_rq_L | 14.117(R)|S601 | 0.000| | 16.764(R)|diml_L | 0.000| md_dir_L | 14.501(R)|S602 | 0.000| skip_L | 14.639(R)|S602 | 0.000| we_L | 12.740(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<7> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 12.112(R)|S602 | 0.000| c1_L | 14.466(R)|S602 | 0.000| data_L<0> | 17.564(R)|S602 | 0.000| data_L<10> | 17.671(R)|S602 | 0.000| data_L<11> | 14.498(R)|S601 | 0.000| | 18.096(R)|S602 | 0.000| data_L<1> | 17.568(R)|S602 | 0.000| data_L<2> | 13.858(R)|S601 | 0.000| | 18.355(R)|S602 | 0.000| data_L<3> | 17.900(R)|S602 | 0.000| | 17.402(R)|diml_L | 0.000| data_L<4> | 19.980(R)|S602 | 0.000| | 18.050(R)|diml_L | 0.000| data_L<5> | 19.351(R)|S602 | 0.000| | 16.869(R)|diml_L | 0.000| data_L<6> | 19.151(R)|S602 | 0.000| | 17.313(R)|diml_L | 0.000| data_L<7> | 18.080(R)|S602 | 0.000| | 16.256(R)|diml_L | 0.000| data_L<8> | 17.721(R)|S602 | 0.000| | 16.424(R)|diml_L | 0.000| data_L<9> | 17.880(R)|S602 | 0.000| int_rq_L | 12.633(R)|S601 | 0.000| | 17.815(R)|diml_L | 0.000| md_dir_L | 13.017(R)|S602 | 0.000| skip_L | 13.155(R)|S602 | 0.000| we_L | 11.256(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<8> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 13.807(R)|S602 | 0.000| c1_L | 16.161(R)|S602 | 0.000| data_L<0> | 19.259(R)|S602 | 0.000| data_L<10> | 19.366(R)|S602 | 0.000| data_L<11> | 16.193(R)|S601 | 0.000| | 19.791(R)|S602 | 0.000| data_L<1> | 19.263(R)|S602 | 0.000| data_L<2> | 15.553(R)|S601 | 0.000| | 20.050(R)|S602 | 0.000| data_L<3> | 19.595(R)|S602 | 0.000| | 15.985(R)|diml_L | 0.000| data_L<4> | 21.675(R)|S602 | 0.000| | 16.633(R)|diml_L | 0.000| data_L<5> | 21.046(R)|S602 | 0.000| | 15.452(R)|diml_L | 0.000| data_L<6> | 20.846(R)|S602 | 0.000| | 15.896(R)|diml_L | 0.000| data_L<7> | 19.775(R)|S602 | 0.000| | 14.839(R)|diml_L | 0.000| data_L<8> | 19.416(R)|S602 | 0.000| | 15.007(R)|diml_L | 0.000| data_L<9> | 19.575(R)|S602 | 0.000| int_rq_L | 14.328(R)|S601 | 0.000| | 16.398(R)|diml_L | 0.000| md_dir_L | 14.712(R)|S602 | 0.000| skip_L | 14.850(R)|S602 | 0.000| we_L | 12.951(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock md_L<9> to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ data_L<3> | 16.140(R)|diml_L | 0.000| data_L<4> | 16.788(R)|diml_L | 0.000| data_L<5> | 15.607(R)|diml_L | 0.000| data_L<6> | 16.051(R)|diml_L | 0.000| data_L<7> | 14.994(R)|diml_L | 0.000| data_L<8> | 15.162(R)|diml_L | 0.000| int_rq_L | 16.553(R)|diml_L | 0.000| ------------+------------+------------------+--------+ Clock overflow_L to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ data_L<7> | 13.110(R)|stop | 0.000| skip_L | 11.347(R)|stop | 0.000| ------------+------------+------------------+--------+ Clock tp1 to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ load_cont_L | 7.286(R)|tp1_BUFGP | 0.000| ------------+------------+------------------+--------+ Clock tp3 to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ c0_L | 12.476(R)|S602 | 0.000| c1_L | 14.830(R)|S602 | 0.000| data_L<0> | 17.928(R)|S602 | 0.000| data_L<10> | 18.035(R)|S602 | 0.000| data_L<11> | 15.173(R)|S601 | 0.000| | 18.460(R)|S602 | 0.000| data_L<1> | 17.932(R)|S602 | 0.000| data_L<2> | 14.533(R)|S601 | 0.000| | 18.719(R)|S602 | 0.000| data_L<3> | 18.264(R)|S602 | 0.000| data_L<4> | 20.344(R)|S602 | 0.000| data_L<5> | 19.715(R)|S602 | 0.000| data_L<6> | 19.515(R)|S602 | 0.000| data_L<7> | 18.444(R)|S602 | 0.000| data_L<8> | 18.085(R)|S602 | 0.000| data_L<9> | 18.244(R)|S602 | 0.000| ema_L<0> | 8.814(R)|tp3_BUFGP | 0.000| ema_L<1> | 8.591(R)|tp3_BUFGP | 0.000| ema_L<2> | 8.918(R)|tp3_BUFGP | 0.000| int_rq_L | 13.308(R)|S601 | 0.000| ma_L<0> | 9.277(R)|tp3_BUFGP | 0.000| ma_L<10> | 9.041(R)|tp3_BUFGP | 0.000| ma_L<11> | 9.194(R)|tp3_BUFGP | 0.000| ma_L<1> | 9.761(R)|tp3_BUFGP | 0.000| ma_L<2> | 8.559(R)|tp3_BUFGP | 0.000| ma_L<3> | 9.543(R)|tp3_BUFGP | 0.000| ma_L<4> | 9.567(R)|tp3_BUFGP | 0.000| ma_L<5> | 9.260(R)|tp3_BUFGP | 0.000| ma_L<6> | 9.392(R)|tp3_BUFGP | 0.000| ma_L<7> | 9.680(R)|tp3_BUFGP | 0.000| ma_L<8> | 9.230(R)|tp3_BUFGP | 0.000| ma_L<9> | 8.378(R)|tp3_BUFGP | 0.000| md_dir_L | 13.381(R)|S602 | 0.000| skip_L | 13.519(R)|S602 | 0.000| we_L | 11.620(R)|S602 | 0.000| ------------+------------+------------------+--------+ Clock tp4 to Pad ---------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ---------------+------------+------------------+--------+ break_cycle_L | 9.241(R)|tp4_BUFGP | 0.000| brk_data_cont_L| 11.120(R)|tp4_BUFGP | 0.000| ema_L<0> | 11.315(R)|tp4_BUFGP | 0.000| ema_L<1> | 11.689(R)|tp4_BUFGP | 0.000| ema_L<2> | 11.314(R)|tp4_BUFGP | 0.000| ma_L<0> | 10.969(R)|tp4_BUFGP | 0.000| ma_L<10> | 11.035(R)|tp4_BUFGP | 0.000| ma_L<11> | 11.343(R)|tp4_BUFGP | 0.000| ma_L<1> | 11.580(R)|tp4_BUFGP | 0.000| ma_L<2> | 11.631(R)|tp4_BUFGP | 0.000| ma_L<3> | 10.871(R)|tp4_BUFGP | 0.000| ma_L<4> | 11.614(R)|tp4_BUFGP | 0.000| ma_L<5> | 11.669(R)|tp4_BUFGP | 0.000| ma_L<6> | 11.261(R)|tp4_BUFGP | 0.000| ma_L<7> | 11.048(R)|tp4_BUFGP | 0.000| ma_L<8> | 11.394(R)|tp4_BUFGP | 0.000| ma_L<9> | 11.343(R)|tp4_BUFGP | 0.000| ms_disable_L | 9.959(R)|tp4_BUFGP | 0.000| ---------------+------------+------------------+--------+ Clock to Setup on destination clock md_L<10> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 3.894| 1.160| | | md_L<3> | 3.894| 2.924| | | md_L<4> | 3.894| 2.964| | | md_L<5> | 3.894| 2.336| | | md_L<6> | 3.894| 2.251| | | md_L<7> | 3.894| 0.767| | | md_L<8> | 3.894| 2.462| | | md_L<9> | 1.105| 1.105| | | tp3 | 3.894| 1.106| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<11> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| | | | md_L<11> | 1.124| 1.124| | | md_L<3> | 4.291| 2.825| | | md_L<4> | 4.291| 2.865| | | md_L<5> | 4.291| 2.237| | | md_L<6> | 4.291| 2.152| | | md_L<7> | 4.291| 0.668| | | md_L<8> | 4.291| 2.363| | | tp3 | 4.291| 1.343| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<3> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| -0.230| | | md_L<11> | -0.237| -0.237| | | md_L<3> | 4.291| 1.534| | | md_L<4> | 4.291| 1.574| | | md_L<5> | 4.291| 0.946| | | md_L<6> | 4.291| 0.861| | | md_L<7> | 4.291| -0.623| | | md_L<8> | 4.291| 1.072| | | md_L<9> | -0.285| -0.285| | | tp3 | 4.291| -0.018| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<4> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| -0.262| | | md_L<11> | -0.269| -0.269| | | md_L<3> | 4.291| 1.502| | | md_L<4> | 4.291| 1.542| | | md_L<5> | 4.291| 0.914| | | md_L<6> | 4.291| 0.829| | | md_L<7> | 4.291| -0.655| | | md_L<8> | 4.291| 1.040| | | md_L<9> | -0.317| -0.317| | | tp3 | 4.291| -0.050| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<5> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| 0.241| | | md_L<11> | 0.234| 0.234| | | md_L<3> | 4.291| 2.005| | | md_L<4> | 4.291| 2.045| | | md_L<5> | 4.291| 1.417| | | md_L<6> | 4.291| 1.332| | | md_L<7> | 4.291| -0.152| | | md_L<8> | 4.291| 1.543| | | md_L<9> | 0.186| 0.186| | | tp3 | 4.291| 0.453| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<6> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| 0.308| | | md_L<11> | 0.301| 0.301| | | md_L<3> | 4.291| 2.072| | | md_L<4> | 4.291| 2.112| | | md_L<5> | 4.291| 1.484| | | md_L<6> | 4.291| 1.399| | | md_L<7> | 4.291| -0.085| | | md_L<8> | 4.291| 1.610| | | md_L<9> | 0.253| 0.253| | | tp3 | 4.291| 0.520| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<7> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| 1.495| | | md_L<11> | 1.488| 1.488| | | md_L<3> | 4.291| 3.259| | | md_L<4> | 4.291| 3.299| | | md_L<5> | 4.291| 2.671| | | md_L<6> | 4.291| 2.586| | | md_L<7> | 4.291| 1.102| | | md_L<8> | 4.291| 2.797| | | md_L<9> | 1.440| 1.440| | | tp3 | 4.291| 1.707| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock md_L<8> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| 0.139| | | md_L<11> | 0.132| 0.132| | | md_L<3> | 4.291| 1.903| | | md_L<4> | 4.291| 1.943| | | md_L<5> | 4.291| 1.315| | | md_L<6> | 4.291| 1.230| | | md_L<7> | 4.291| -0.254| | | md_L<8> | 4.291| 1.441| | | md_L<9> | 0.084| 0.084| | | tp3 | 4.291| 0.351| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock overflow_L ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.182| 2.473| | | md_L<11> | 3.351| | | | md_L<3> | 4.695| 4.695| | | md_L<4> | 4.735| 4.735| | | md_L<5> | 4.182| 4.107| | | md_L<6> | 4.182| 4.022| | | md_L<7> | 4.182| 2.538| | | md_L<8> | 4.233| 4.233| | | md_L<9> | 2.334| 2.334| | | overflow_L | 1.357| 1.357| | | tp3 | 4.182| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock tp1 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ tp1 | 2.242| 2.242| | | tp4 | 5.556| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock tp3 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ md_L<10> | 4.291| 3.003| | | md_L<11> | 3.001| 3.001| | | md_L<3> | 4.291| 2.959| | | md_L<4> | 4.291| 2.959| | | md_L<5> | 4.291| 2.961| | | md_L<6> | 4.291| 2.959| | | md_L<7> | 4.291| 2.961| | | md_L<8> | 4.291| 2.982| | | md_L<9> | 3.017| 3.017| | | tp3 | 4.291| 3.666| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock tp4 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ overflow_L | 4.727| | | | tp4 | 1.897| 1.897| | | ---------------+---------+---------+---------+---------+ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ md_L<0> |data_L<0> | 9.486| md_L<10> |c0_L | 10.590| md_L<10> |data_L<0> | 10.964| md_L<10> |data_L<10> | 11.071| md_L<10> |data_L<11> | 11.496| md_L<10> |data_L<1> | 10.968| md_L<10> |data_L<2> | 11.755| md_L<10> |data_L<3> | 11.300| md_L<10> |data_L<4> | 13.380| md_L<10> |data_L<5> | 12.751| md_L<10> |data_L<6> | 12.551| md_L<10> |data_L<7> | 11.480| md_L<10> |data_L<8> | 11.121| md_L<10> |data_L<9> | 11.280| md_L<10> |skip_L | 8.646| md_L<11> |c0_L | 9.944| md_L<11> |c1_L | 10.261| md_L<11> |data_L<0> | 12.583| md_L<11> |data_L<10> | 13.054| md_L<11> |data_L<11> | 12.915| md_L<11> |data_L<1> | 12.587| md_L<11> |data_L<2> | 12.886| md_L<11> |data_L<3> | 12.919| md_L<11> |data_L<4> | 15.065| md_L<11> |data_L<5> | 14.436| md_L<11> |data_L<6> | 14.236| md_L<11> |data_L<7> | 12.640| md_L<11> |data_L<8> | 12.806| md_L<11> |data_L<9> | 13.263| md_L<11> |skip_L | 9.545| md_L<1> |data_L<1> | 8.897| md_L<2> |data_L<2> | 9.402| md_L<3> |c0_L | 12.494| md_L<3> |c1_L | 11.539| md_L<3> |data_L<0> | 14.022| md_L<3> |data_L<10> | 14.129| md_L<3> |data_L<11> | 14.554| md_L<3> |data_L<1> | 14.026| md_L<3> |data_L<2> | 14.813| md_L<3> |data_L<3> | 14.358| md_L<3> |data_L<4> | 16.438| md_L<3> |data_L<5> | 15.809| md_L<3> |data_L<6> | 15.609| md_L<3> |data_L<7> | 14.538| md_L<3> |data_L<8> | 14.179| md_L<3> |data_L<9> | 14.338| md_L<3> |skip_L | 10.452| md_L<4> |c0_L | 12.710| md_L<4> |c1_L | 11.579| md_L<4> |data_L<0> | 14.238| md_L<4> |data_L<10> | 14.345| md_L<4> |data_L<11> | 14.770| md_L<4> |data_L<1> | 14.242| md_L<4> |data_L<2> | 15.029| md_L<4> |data_L<3> | 14.574| md_L<4> |data_L<4> | 16.654| md_L<4> |data_L<5> | 16.025| md_L<4> |data_L<6> | 15.825| md_L<4> |data_L<7> | 14.754| md_L<4> |data_L<8> | 14.395| md_L<4> |data_L<9> | 14.554| md_L<4> |skip_L | 10.668| md_L<5> |c0_L | 12.870| md_L<5> |c1_L | 11.508| md_L<5> |data_L<0> | 14.398| md_L<5> |data_L<10> | 14.505| md_L<5> |data_L<11> | 14.930| md_L<5> |data_L<1> | 14.402| md_L<5> |data_L<2> | 15.189| md_L<5> |data_L<3> | 14.734| md_L<5> |data_L<4> | 16.814| md_L<5> |data_L<5> | 16.185| md_L<5> |data_L<6> | 15.985| md_L<5> |data_L<7> | 14.914| md_L<5> |data_L<8> | 14.555| md_L<5> |data_L<9> | 14.714| md_L<5> |skip_L | 10.828| md_L<6> |c0_L | 10.111| md_L<6> |c1_L | 10.866| md_L<6> |data_L<0> | 12.728| md_L<6> |data_L<10> | 12.835| md_L<6> |data_L<11> | 13.260| md_L<6> |data_L<1> | 12.732| md_L<6> |data_L<2> | 13.519| md_L<6> |data_L<3> | 13.064| md_L<6> |data_L<4> | 15.144| md_L<6> |data_L<5> | 14.515| md_L<6> |data_L<6> | 14.315| md_L<6> |data_L<7> | 13.244| md_L<6> |data_L<8> | 12.885| md_L<6> |data_L<9> | 13.044| md_L<6> |skip_L | 9.158| md_L<7> |c0_L | 12.251| md_L<7> |c1_L | 10.889| md_L<7> |data_L<0> | 13.779| md_L<7> |data_L<10> | 13.886| md_L<7> |data_L<11> | 14.311| md_L<7> |data_L<1> | 13.783| md_L<7> |data_L<2> | 14.570| md_L<7> |data_L<3> | 14.115| md_L<7> |data_L<4> | 16.195| md_L<7> |data_L<5> | 15.566| md_L<7> |data_L<6> | 15.366| md_L<7> |data_L<7> | 14.295| md_L<7> |data_L<8> | 13.936| md_L<7> |data_L<9> | 14.095| md_L<7> |skip_L | 10.209| md_L<8> |c0_L | 9.717| md_L<8> |c1_L | 11.077| md_L<8> |data_L<0> | 12.379| md_L<8> |data_L<10> | 12.827| md_L<8> |data_L<11> | 12.894| md_L<8> |data_L<1> | 12.366| md_L<8> |data_L<2> | 13.256| md_L<8> |data_L<3> | 12.968| md_L<8> |data_L<4> | 14.838| md_L<8> |data_L<5> | 14.209| md_L<8> |data_L<6> | 14.009| md_L<8> |data_L<7> | 12.878| md_L<8> |data_L<8> | 12.579| md_L<8> |data_L<9> | 13.036| md_L<8> |skip_L | 9.065| md_L<9> |c0_L | 8.984| md_L<9> |c1_L | 10.575| md_L<9> |data_L<0> | 12.517| md_L<9> |data_L<10> | 12.624| md_L<9> |data_L<11> | 13.049| md_L<9> |data_L<1> | 12.521| md_L<9> |data_L<2> | 13.308| md_L<9> |data_L<3> | 12.853| md_L<9> |data_L<4> | 14.933| md_L<9> |data_L<5> | 14.304| md_L<9> |data_L<6> | 14.104| md_L<9> |data_L<7> | 13.033| md_L<9> |data_L<8> | 12.674| md_L<9> |data_L<9> | 12.833| md_L<9> |skip_L | 8.102| pca_L |data_L<0> | 9.460| pca_L |int_rq_L | 9.335| protect |we_L | 6.541| ts4_L |data_L<7> | 11.206| word_L |data_L<7> | 10.468| ---------------+---------------+---------+ Analysis completed Fri Apr 18 08:23:46 2014 -------------------------------------------------------------------------------- Peak Memory Usage: 131 MB