Timing Report

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Design Name	rf08
Device, Speed (SpeedFile Version)	XC95288XL, -6 (3.0)
Date Created	Fri Apr 18 19:37:25 2014
Created By	Timing Report Generator: version H.38
Copyright	Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'per.CLKF' has multiple original clock nets 'md_L<11>' 'md_L<3>' 'md_L<7>' 'md_L<8>' 'md_L<5>' 'writing.Q' 'md_L<4>' 'tp3' 'md_L<6>' 'dt.Q'.
Possible asynchronous logic: Clock pin 'wls.CLKF' has multiple original clock nets 'md_L<11>' 'md_L<3>' 'md_L<7>' 'md_L<8>' 'md_L<5>' 'writing.Q' 'md_L<4>' 'tp3' 'md_L<6>' 'dt.Q'.
Possible asynchronous logic: Clock pin 'busy.CLKF' has multiple original clock nets 'overflow_L' 'wc.Q' 'wls.Q' 'per.Q'.
Possible asynchronous logic: Clock pin 'writing.CLKF' has multiple original clock nets 'md_L<3>' 'md_L<10>' 'md_L<7>' 'md_L<8>' 'md_L<5>' 'writing.Q' 'md_L<4>' 'tp3' 'md_L<6>' 'dt.Q'.

Performance Summary
Min. Clock Period	12.000 ns.
Max. Clock Frequency (fSYSTEM)	83.333 MHz.
Limited by Clock Pulse Width for busy.Q
Clock to Setup (tCYC)	8.900 ns.
Pad to Pad Delay (tPD)	15.500 ns.
Setup to Clock at the Pad (tSU)	5.100 ns.
Clock Pad to Output Pad Delay (tCO)	41.800 ns.

Timing Constraints

Constraint Name	Delay (ns)	Paths	Paths Failing
TS1000	0.0	0	0
TS1001	0.0	0	0
TS1002	0.0	0	0
TS1003	0.0	0	0
TS1004	0.0	0	0
TS1005	0.0	0	0
TS1006	0.0	0	0
TS1007	0.0	0	0
TS1008	0.0	0	0
TS1009	0.0	0	0
TS1010	0.0	0	0
TS1011	0.0	0	0
TS1012	0.0	0	0
TS1013	0.0	0	0
TS1014	0.0	0	0
TS1015	0.0	0	0
TS1016	0.0	0	0
TS1017	0.0	0	0
TS1018	0.0	0	0
AUTO_TS_F2F	8.9	311	311
AUTO_TS_P2P	41.8	387	387
AUTO_TS_P2F	9.3	406	406
AUTO_TS_F2P	15.1	136	136

Constraint: TS1000

**Description: PERIOD:PERIOD_tp1:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1001

**Description: PERIOD:PERIOD_tp4:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1002

**Description: PERIOD:PERIOD_busy.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1003

**Description: PERIOD:PERIOD_md_L<11>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1004

**Description: PERIOD:PERIOD_overflow_L:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1005

**Description: PERIOD:PERIOD_wc.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1006

**Description: PERIOD:PERIOD_wls.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1007

**Description: PERIOD:PERIOD_per.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1008

**Description: PERIOD:PERIOD_md_L<3>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1009

**Description: PERIOD:PERIOD_md_L<10>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1010

**Description: PERIOD:PERIOD_md_L<7>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1011

**Description: PERIOD:PERIOD_md_L<8>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1012

**Description: PERIOD:PERIOD_md_L<5>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1013

**Description: PERIOD:PERIOD_writing.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1014

**Description: PERIOD:PERIOD_md_L<4>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1015

**Description: PERIOD:PERIOD_tp3:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1016

**Description: PERIOD:PERIOD_md_L<6>:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1017

**Description: PERIOD:PERIOD_my_db.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1018

**Description: PERIOD:PERIOD_dt.Q:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_F2F

**Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
dt.Q to dtema_L<0>.D	8.900	-8.900
dt.Q to dtema_L<1>.D	8.900	-8.900
dt.Q to dtema_L<2>.D	8.900	-8.900

Constraint: AUTO_TS_P2P

**Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
tp4 to int_rq_L	41.800	-41.800
tp4 to data_L<7>	38.000	-38.000
md_L<7> to int_rq_L	37.200	-37.200

Constraint: AUTO_TS_P2F

**Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
md_L<10> to dtema_L<0>.D	9.300	-9.300
md_L<10> to dtema_L<1>.D	9.300	-9.300
md_L<10> to dtema_L<2>.D	9.300	-9.300

Constraint: AUTO_TS_F2P

**Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
dt.Q to int_rq_L	15.100	-15.100
writing.Q to int_rq_L	15.100	-15.100
busy.Q to data_L<7>	11.000	-11.000

Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock	fEXT (MHz)	Reason
tp1	208.333	Limited by Clock Pulse Width for tp1
tp4	208.333	Limited by Clock Pulse Width for tp4
busy.Q	83.333	Limited by Clock Pulse Width for busy.Q
md_L<11>	83.333	Limited by Clock Pulse Width for md_L<11>
overflow_L	83.333	Limited by Clock Pulse Width for overflow_L
wc.Q	83.333	Limited by Clock Pulse Width for wc.Q
wls.Q	83.333	Limited by Clock Pulse Width for wls.Q
per.Q	83.333	Limited by Clock Pulse Width for per.Q
md_L<3>	83.333	Limited by Clock Pulse Width for md_L<3>
md_L<10>	83.333	Limited by Clock Pulse Width for md_L<10>
md_L<7>	83.333	Limited by Clock Pulse Width for md_L<7>
md_L<8>	83.333	Limited by Clock Pulse Width for md_L<8>
md_L<5>	83.333	Limited by Clock Pulse Width for md_L<5>
writing.Q	83.333	Limited by Clock Pulse Width for writing.Q
md_L<4>	83.333	Limited by Clock Pulse Width for md_L<4>
tp3	83.333	Limited by Clock Pulse Width for tp3
md_L<6>	83.333	Limited by Clock Pulse Width for md_L<6>
my_db.Q	83.333	Limited by Clock Pulse Width for my_db.Q
dt.Q	83.333	Limited by Clock Pulse Width for dt.Q

Setup/Hold Times for Clocks

**Setup/Hold Times for Clock tp1**
Source Pad	Setup to clk (edge)	Hold to clk (edge)

**Setup/Hold Times for Clock tp4**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
data_L<0>	4.000	0.000
data_L<1>	4.000	0.000
data_L<2>	4.000	0.000
data_L<3>	4.000	0.000
data_L<4>	4.000	0.000
data_L<5>	4.000	0.000
data_L<6>	4.000	0.000
word_L	4.000	0.000

**Setup/Hold Times for Clock busy.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
md_L<11>	2.200	0.000
md_L<3>	2.200	0.000
md_L<4>	2.200	0.000
md_L<5>	2.200	0.000
md_L<6>	2.200	0.000
md_L<7>	2.200	0.000
md_L<8>	2.200	0.000
tp3	2.200	0.000

**Setup/Hold Times for Clock md_L<11>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<3>	-2.000	3.600
md_L<4>	-2.000	3.600
md_L<5>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<8>	-2.000	3.600
protect	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock overflow_L**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-1.200	2.800
md_L<10>	-2.000	3.600
md_L<3>	-1.200	2.800
md_L<4>	-1.200	2.800
md_L<5>	-1.200	2.800
md_L<6>	-1.200	2.800
md_L<7>	-1.200	2.800
md_L<8>	-1.200	2.800
md_L<9>	-1.200	2.800

**Setup/Hold Times for Clock wc.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-0.800	2.400
md_L<10>	-1.600	3.200
md_L<3>	-0.800	2.400
md_L<4>	-0.800	2.400
md_L<5>	-0.800	2.400
md_L<6>	-0.800	2.400
md_L<7>	-0.800	2.400
md_L<8>	-0.800	2.400
md_L<9>	-0.800	2.400
overflow_L	-1.600	3.200

**Setup/Hold Times for Clock wls.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-0.800	2.400
md_L<10>	-1.600	3.200
md_L<3>	-0.800	2.400
md_L<4>	-0.800	2.400
md_L<5>	-0.800	2.400
md_L<6>	-0.800	2.400
md_L<7>	-0.800	2.400
md_L<8>	-0.800	2.400
md_L<9>	-0.800	2.400
overflow_L	-1.600	3.200

**Setup/Hold Times for Clock per.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-0.800	2.400
md_L<10>	-1.600	3.200
md_L<3>	-0.800	2.400
md_L<4>	-0.800	2.400
md_L<5>	-0.800	2.400
md_L<6>	-0.800	2.400
md_L<7>	-0.800	2.400
md_L<8>	-0.800	2.400
md_L<9>	-0.800	2.400
overflow_L	-1.600	3.200

**Setup/Hold Times for Clock md_L<3>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<10>	-2.000	3.600
md_L<11>	-2.000	3.600
md_L<4>	-2.000	3.600
md_L<5>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<8>	-2.000	3.600
md_L<9>	-2.000	3.600
protect	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock md_L<10>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<3>	-2.000	3.600
md_L<4>	-2.000	3.600
md_L<5>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<8>	-2.000	3.600
md_L<9>	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock md_L<7>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.800	4.400
md_L<10>	-2.800	4.400
md_L<11>	-2.800	4.400
md_L<3>	-2.800	4.400
md_L<4>	-2.800	4.400
md_L<5>	-2.800	4.400
md_L<6>	-2.800	4.400
md_L<8>	-2.800	4.400
md_L<9>	-2.800	4.400
protect	-2.800	4.400
tp3	-2.800	4.400

**Setup/Hold Times for Clock md_L<8>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<10>	-2.000	3.600
md_L<11>	-2.000	3.600
md_L<3>	-2.000	3.600
md_L<4>	-2.000	3.600
md_L<5>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<9>	-2.000	3.600
protect	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock md_L<5>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<10>	-2.000	3.600
md_L<11>	-2.000	3.600
md_L<3>	-2.000	3.600
md_L<4>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<8>	-2.000	3.600
md_L<9>	-2.000	3.600
protect	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock writing.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-1.600	3.200
md_L<10>	-1.600	3.200
md_L<11>	-1.600	3.200
md_L<3>	-1.600	3.200
md_L<4>	-1.600	3.200
md_L<5>	-1.600	3.200
md_L<6>	-1.600	3.200
md_L<7>	-1.600	3.200
md_L<8>	-1.600	3.200
md_L<9>	-1.600	3.200
protect	-1.600	3.200
tp3	-1.600	3.200

**Setup/Hold Times for Clock md_L<4>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	-2.000	3.600
md_L<10>	-2.000	3.600
md_L<11>	-2.000	3.600
md_L<3>	-2.000	3.600
md_L<5>	-2.000	3.600
md_L<6>	-2.000	3.600
md_L<7>	-2.000	3.600
md_L<8>	-2.000	3.600
md_L<9>	-2.000	3.600
protect	-2.000	3.600
tp3	-2.000	3.600

**Setup/Hold Times for Clock tp3**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
data_L<6>	4.500	0.000
data_L<7>	4.500	0.000
data_L<8>	4.500	0.000
initialize	1.000	0.600
md_L<0>	1.000	0.600
md_L<10>	5.100	0.600
md_L<11>	5.100	0.600
md_L<1>	1.000	0.600
md_L<2>	1.000	0.600
md_L<3>	5.100	0.600
md_L<4>	5.100	0.600
md_L<5>	5.100	0.600
md_L<6>	5.100	0.600
md_L<7>	5.100	0.600
md_L<8>	5.100	0.600
md_L<9>	5.100	0.600
protect	1.000	0.600

**Setup/Hold Times for Clock md_L<6>**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	1.000	0.600
md_L<10>	1.000	0.600
md_L<11>	1.000	0.600
md_L<3>	1.000	0.600
md_L<4>	1.000	0.600
md_L<5>	1.000	0.600
md_L<7>	1.000	0.600
md_L<8>	1.000	0.600
md_L<9>	1.000	0.600
protect	1.000	0.600
tp3	1.000	0.600

**Setup/Hold Times for Clock my_db.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
initialize	2.200	0.200
word_L	1.400	0.200

**Setup/Hold Times for Clock dt.Q**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
data_L<0>	2.200	0.000
data_L<10>	2.200	0.000
data_L<11>	2.200	0.000
data_L<1>	2.200	0.000
data_L<2>	2.200	0.000
data_L<3>	2.200	0.000
data_L<4>	2.500	0.000
data_L<5>	2.200	0.000
data_L<6>	2.200	0.000
data_L<7>	2.200	0.000
data_L<8>	2.200	0.000
data_L<9>	2.200	0.000
initialize	2.500	3.200
md_L<10>	2.500	3.200
md_L<11>	2.500	3.200
md_L<3>	2.500	3.200
md_L<4>	2.500	3.200
md_L<5>	2.500	3.200
md_L<6>	2.500	3.200
md_L<7>	2.500	3.200
md_L<8>	2.500	3.200
md_L<9>	2.500	3.200
protect	-1.600	3.200
tp3	-1.600	3.200

Clock to Pad Timing

**Clock tp1 to Pad**
Destination Pad	Clock (edge) to Pad
load_cont_L	9.200

**Clock tp4 to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	41.800
data_L<7>	38.000
skip_L	33.400
data_L<11>	26.600
data_L<2>	26.600
data_L<4>	23.100
data_L<5>	23.100
data_L<6>	23.100
data_L<8>	23.100
data_L<3>	22.300
data_L<0>	20.600
data_L<10>	20.600
data_L<1>	20.600
data_L<9>	20.600
md_dir_L	20.600
c0_L	19.300
c1_L	18.200
we_L	18.200
ema_L<0>	13.000
ema_L<1>	13.000
ema_L<2>	13.000
ma_L<0>	13.000
ma_L<10>	13.000
ma_L<11>	13.000
ma_L<1>	13.000
ma_L<2>	13.000
ma_L<3>	13.000
ma_L<4>	13.000
ma_L<5>	13.000
ma_L<6>	13.000
ma_L<7>	13.000
ma_L<8>	13.000
ma_L<9>	13.000
cs0_L	11.400
cs1_L	11.400
dar<10>	11.400
dar<11>	11.400
dar<4>	11.400
dar<5>	11.400
dar<6>	11.400
dar<7>	11.400
dar<8>	11.400
dar<9>	11.400
dma<0>	11.400
dma<10>	11.400
dma<11>	11.400
dma<1>	11.400
dma<2>	11.400
dma<3>	11.400
dma<4>	11.400
dma<5>	11.400
dma<6>	11.400
dma<7>	11.400
dma<8>	11.400
dma<9>	11.400
brk_data_cont_L	10.600
break_cycle_L	9.200
ms_disable_L	9.200

**Clock md_L<11> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	28.800
data_L<7>	25.000
skip_L	20.400
data_L<11>	13.600
data_L<2>	13.600

**Clock overflow_L to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	22.000
data_L<7>	18.200
skip_L	13.600

**Clock md_L<3> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

**Clock md_L<10> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

**Clock md_L<7> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	37.200
data_L<7>	33.400
skip_L	28.800
data_L<11>	22.000
data_L<2>	22.000
data_L<4>	18.500
data_L<5>	18.500
data_L<6>	18.500
data_L<8>	18.500
data_L<3>	17.700
data_L<0>	16.000
data_L<10>	16.000
data_L<1>	16.000
data_L<9>	16.000
md_dir_L	16.000
c0_L	14.700
c1_L	13.600
we_L	13.600

**Clock md_L<8> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

**Clock md_L<5> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

**Clock md_L<4> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

**Clock tp3 to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200
ema_L<0>	9.800
ema_L<1>	9.800
ema_L<2>	9.800
ma_L<0>	9.800
ma_L<10>	9.800
ma_L<11>	9.800
ma_L<1>	9.800
ma_L<2>	9.800
ma_L<3>	9.800
ma_L<4>	9.800
ma_L<5>	9.800
ma_L<6>	9.800
ma_L<7>	9.800
ma_L<8>	9.800
ma_L<9>	9.800

**Clock md_L<6> to Pad**
Destination Pad	Clock (edge) to Pad
int_rq_L	36.800
data_L<7>	33.000
skip_L	28.400
data_L<11>	21.600
data_L<2>	21.600
data_L<4>	18.100
data_L<5>	18.100
data_L<6>	18.100
data_L<8>	18.100
data_L<3>	17.300
data_L<0>	15.600
data_L<10>	15.600
data_L<1>	15.600
data_L<9>	15.600
md_dir_L	15.600
c0_L	14.300
c1_L	13.200
we_L	13.200

Clock to Setup Times for Clocks

**Clock to Setup for clock busy.Q**
Source	Destination	Delay
done.Q	done.D	5.600

**Clock to Setup for clock md_L<11>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800

**Clock to Setup for clock overflow_L**
Source	Destination	Delay
busy.Q	busy.D	4.800

**Clock to Setup for clock wc.Q**
Source	Destination	Delay
busy.Q	busy.D	4.800

**Clock to Setup for clock wls.Q**
Source	Destination	Delay
busy.Q	busy.D	4.800

**Clock to Setup for clock per.Q**
Source	Destination	Delay
busy.Q	busy.D	4.800

**Clock to Setup for clock md_L<3>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<10>**
Source	Destination	Delay
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<7>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<8>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<5>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock writing.Q**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<4>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock tp3**
Source	Destination	Delay
writing.Q	dtema_L<0>.D	8.900
writing.Q	dtema_L<1>.D	8.900
writing.Q	dtema_L<2>.D	8.900
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock md_L<6>**
Source	Destination	Delay
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

**Clock to Setup for clock my_db.Q**
Source	Destination	Delay
dt.Q	idle.D	5.600
idle.Q	idle.D	5.600
ca.Q	ca.D	4.800
ca.Q	dt.D	4.800
dt.Q	dt.D	4.800
wc.Q	ca.D	4.800
wc.Q	wc.D	4.800

**Clock to Setup for clock dt.Q**
Source	Destination	Delay
dar<10>.Q	cs0_L.D	5.900
dar<10>.Q	cs1_L.D	5.900
dar<11>.Q	cs0_L.D	5.900
dar<11>.Q	cs1_L.D	5.900
dar<4>.Q	cs0_L.D	5.900
dar<4>.Q	cs1_L.D	5.900
dar<5>.Q	cs0_L.D	5.900
dar<5>.Q	cs1_L.D	5.900
dar<6>.Q	cs0_L.D	5.900
dar<6>.Q	cs1_L.D	5.900
dar<7>.Q	cs0_L.D	5.900
dar<7>.Q	cs1_L.D	5.900
dar<8>.Q	cs0_L.D	5.900
dar<8>.Q	cs1_L.D	5.900
dar<9>.Q	cs0_L.D	5.900
dar<9>.Q	cs1_L.D	5.900
dma<0>.Q	cs0_L.D	5.900
dma<0>.Q	cs1_L.D	5.900
dma<10>.Q	cs0_L.D	5.900
dma<10>.Q	cs1_L.D	5.900
dma<11>.Q	cs0_L.D	5.900
dma<11>.Q	cs1_L.D	5.900
dma<1>.Q	cs0_L.D	5.900
dma<1>.Q	cs1_L.D	5.900
dma<2>.Q	cs0_L.D	5.900
dma<2>.Q	cs1_L.D	5.900
dma<3>.Q	cs0_L.D	5.900
dma<3>.Q	cs1_L.D	5.900
dma<4>.Q	cs0_L.D	5.900
dma<4>.Q	cs1_L.D	5.900
dma<5>.Q	cs0_L.D	5.900
dma<5>.Q	cs1_L.D	5.900
dma<6>.Q	cs0_L.D	5.900
dma<6>.Q	cs1_L.D	5.900
dma<7>.Q	cs0_L.D	5.900
dma<7>.Q	cs1_L.D	5.900
dma<8>.Q	cs0_L.D	5.900
dma<8>.Q	cs1_L.D	5.900
dma<9>.Q	cs0_L.D	5.900
dma<9>.Q	cs1_L.D	5.900
dar<10>.Q	dar<10>.D	5.600
dar<11>.Q	dar<11>.D	5.600
dar<4>.Q	dar<4>.D	5.600
dar<5>.Q	dar<5>.D	5.600
dar<6>.Q	dar<6>.D	5.600
dar<7>.Q	dar<7>.D	5.600
dar<8>.Q	dar<8>.D	5.600
dar<9>.Q	dar<9>.D	5.600
dma<0>.Q	dma<0>.D	5.600
dma<10>.Q	dma<10>.D	5.600
dma<11>.Q	dma<11>.D	5.600
dma<1>.Q	dma<1>.D	5.600
dma<2>.Q	dma<2>.D	5.600
dma<3>.Q	dma<3>.D	5.600
dma<4>.Q	dma<4>.D	5.600
dma<5>.Q	dma<5>.D	5.600
dma<6>.Q	dma<6>.D	5.600
dma<7>.Q	dma<7>.D	5.600
dma<8>.Q	dma<8>.D	5.600
dma<9>.Q	dma<9>.D	5.600
dar<10>.Q	dar<4>.D	4.800
dar<10>.Q	dar<5>.D	4.800
dar<10>.Q	dar<6>.D	4.800
dar<10>.Q	dar<7>.D	4.800
dar<10>.Q	dar<8>.D	4.800
dar<10>.Q	dar<9>.D	4.800
dar<11>.Q	dar<10>.D	4.800
dar<11>.Q	dar<4>.D	4.800
dar<11>.Q	dar<5>.D	4.800
dar<11>.Q	dar<6>.D	4.800
dar<11>.Q	dar<7>.D	4.800
dar<11>.Q	dar<8>.D	4.800
dar<11>.Q	dar<9>.D	4.800
dar<5>.Q	dar<4>.D	4.800
dar<6>.Q	dar<4>.D	4.800
dar<6>.Q	dar<5>.D	4.800
dar<7>.Q	dar<4>.D	4.800
dar<7>.Q	dar<5>.D	4.800
dar<7>.Q	dar<6>.D	4.800
dar<8>.Q	dar<4>.D	4.800
dar<8>.Q	dar<5>.D	4.800
dar<8>.Q	dar<6>.D	4.800
dar<8>.Q	dar<7>.D	4.800
dar<9>.Q	dar<4>.D	4.800
dar<9>.Q	dar<5>.D	4.800
dar<9>.Q	dar<6>.D	4.800
dar<9>.Q	dar<7>.D	4.800
dar<9>.Q	dar<8>.D	4.800
dma<0>.Q	dar<10>.D	4.800
dma<0>.Q	dar<11>.D	4.800
dma<0>.Q	dar<4>.D	4.800
dma<0>.Q	dar<5>.D	4.800
dma<0>.Q	dar<6>.D	4.800
dma<0>.Q	dar<7>.D	4.800
dma<0>.Q	dar<8>.D	4.800
dma<0>.Q	dar<9>.D	4.800
dma<10>.Q	dar<10>.D	4.800
dma<10>.Q	dar<11>.D	4.800
dma<10>.Q	dar<4>.D	4.800
dma<10>.Q	dar<5>.D	4.800
dma<10>.Q	dar<6>.D	4.800
dma<10>.Q	dar<7>.D	4.800
dma<10>.Q	dar<8>.D	4.800
dma<10>.Q	dar<9>.D	4.800
dma<10>.Q	dma<0>.D	4.800
dma<10>.Q	dma<1>.D	4.800
dma<10>.Q	dma<2>.D	4.800
dma<10>.Q	dma<3>.D	4.800
dma<10>.Q	dma<4>.D	4.800
dma<10>.Q	dma<5>.D	4.800
dma<10>.Q	dma<6>.D	4.800
dma<10>.Q	dma<7>.D	4.800
dma<10>.Q	dma<8>.D	4.800
dma<10>.Q	dma<9>.D	4.800
dma<11>.Q	dar<10>.D	4.800
dma<11>.Q	dar<11>.D	4.800
dma<11>.Q	dar<4>.D	4.800
dma<11>.Q	dar<5>.D	4.800
dma<11>.Q	dar<6>.D	4.800
dma<11>.Q	dar<7>.D	4.800
dma<11>.Q	dar<8>.D	4.800
dma<11>.Q	dar<9>.D	4.800
dma<11>.Q	dma<0>.D	4.800
dma<11>.Q	dma<10>.D	4.800
dma<11>.Q	dma<1>.D	4.800
dma<11>.Q	dma<2>.D	4.800
dma<11>.Q	dma<3>.D	4.800
dma<11>.Q	dma<4>.D	4.800
dma<11>.Q	dma<5>.D	4.800
dma<11>.Q	dma<6>.D	4.800
dma<11>.Q	dma<7>.D	4.800
dma<11>.Q	dma<8>.D	4.800
dma<11>.Q	dma<9>.D	4.800
dma<1>.Q	dar<10>.D	4.800
dma<1>.Q	dar<11>.D	4.800
dma<1>.Q	dar<4>.D	4.800
dma<1>.Q	dar<5>.D	4.800
dma<1>.Q	dar<6>.D	4.800
dma<1>.Q	dar<7>.D	4.800
dma<1>.Q	dar<8>.D	4.800
dma<1>.Q	dar<9>.D	4.800
dma<1>.Q	dma<0>.D	4.800
dma<2>.Q	dar<10>.D	4.800
dma<2>.Q	dar<11>.D	4.800
dma<2>.Q	dar<4>.D	4.800
dma<2>.Q	dar<5>.D	4.800
dma<2>.Q	dar<6>.D	4.800
dma<2>.Q	dar<7>.D	4.800
dma<2>.Q	dar<8>.D	4.800
dma<2>.Q	dar<9>.D	4.800
dma<2>.Q	dma<0>.D	4.800
dma<2>.Q	dma<1>.D	4.800
dma<3>.Q	dar<10>.D	4.800
dma<3>.Q	dar<11>.D	4.800
dma<3>.Q	dar<4>.D	4.800
dma<3>.Q	dar<5>.D	4.800
dma<3>.Q	dar<6>.D	4.800
dma<3>.Q	dar<7>.D	4.800
dma<3>.Q	dar<8>.D	4.800
dma<3>.Q	dar<9>.D	4.800
dma<3>.Q	dma<0>.D	4.800
dma<3>.Q	dma<1>.D	4.800
dma<3>.Q	dma<2>.D	4.800
dma<4>.Q	dar<10>.D	4.800
dma<4>.Q	dar<11>.D	4.800
dma<4>.Q	dar<4>.D	4.800
dma<4>.Q	dar<5>.D	4.800
dma<4>.Q	dar<6>.D	4.800
dma<4>.Q	dar<7>.D	4.800
dma<4>.Q	dar<8>.D	4.800
dma<4>.Q	dar<9>.D	4.800
dma<4>.Q	dma<0>.D	4.800
dma<4>.Q	dma<1>.D	4.800
dma<4>.Q	dma<2>.D	4.800
dma<4>.Q	dma<3>.D	4.800
dma<5>.Q	dar<10>.D	4.800
dma<5>.Q	dar<11>.D	4.800
dma<5>.Q	dar<4>.D	4.800
dma<5>.Q	dar<5>.D	4.800
dma<5>.Q	dar<6>.D	4.800
dma<5>.Q	dar<7>.D	4.800
dma<5>.Q	dar<8>.D	4.800
dma<5>.Q	dar<9>.D	4.800
dma<5>.Q	dma<0>.D	4.800
dma<5>.Q	dma<1>.D	4.800
dma<5>.Q	dma<2>.D	4.800
dma<5>.Q	dma<3>.D	4.800
dma<5>.Q	dma<4>.D	4.800
dma<6>.Q	dar<10>.D	4.800
dma<6>.Q	dar<11>.D	4.800
dma<6>.Q	dar<4>.D	4.800
dma<6>.Q	dar<5>.D	4.800
dma<6>.Q	dar<6>.D	4.800
dma<6>.Q	dar<7>.D	4.800
dma<6>.Q	dar<8>.D	4.800
dma<6>.Q	dar<9>.D	4.800
dma<6>.Q	dma<0>.D	4.800
dma<6>.Q	dma<1>.D	4.800
dma<6>.Q	dma<2>.D	4.800
dma<6>.Q	dma<3>.D	4.800
dma<6>.Q	dma<4>.D	4.800
dma<6>.Q	dma<5>.D	4.800
dma<7>.Q	dar<10>.D	4.800
dma<7>.Q	dar<11>.D	4.800
dma<7>.Q	dar<4>.D	4.800
dma<7>.Q	dar<5>.D	4.800
dma<7>.Q	dar<6>.D	4.800
dma<7>.Q	dar<7>.D	4.800
dma<7>.Q	dar<8>.D	4.800
dma<7>.Q	dar<9>.D	4.800
dma<7>.Q	dma<0>.D	4.800
dma<7>.Q	dma<1>.D	4.800
dma<7>.Q	dma<2>.D	4.800
dma<7>.Q	dma<3>.D	4.800
dma<7>.Q	dma<4>.D	4.800
dma<7>.Q	dma<5>.D	4.800
dma<7>.Q	dma<6>.D	4.800
dma<8>.Q	dar<10>.D	4.800
dma<8>.Q	dar<11>.D	4.800
dma<8>.Q	dar<4>.D	4.800
dma<8>.Q	dar<5>.D	4.800
dma<8>.Q	dar<6>.D	4.800
dma<8>.Q	dar<7>.D	4.800
dma<8>.Q	dar<8>.D	4.800
dma<8>.Q	dar<9>.D	4.800
dma<8>.Q	dma<0>.D	4.800
dma<8>.Q	dma<1>.D	4.800
dma<8>.Q	dma<2>.D	4.800
dma<8>.Q	dma<3>.D	4.800
dma<8>.Q	dma<4>.D	4.800
dma<8>.Q	dma<5>.D	4.800
dma<8>.Q	dma<6>.D	4.800
dma<8>.Q	dma<7>.D	4.800
dma<9>.Q	dar<10>.D	4.800
dma<9>.Q	dar<11>.D	4.800
dma<9>.Q	dar<4>.D	4.800
dma<9>.Q	dar<5>.D	4.800
dma<9>.Q	dar<6>.D	4.800
dma<9>.Q	dar<7>.D	4.800
dma<9>.Q	dar<8>.D	4.800
dma<9>.Q	dar<9>.D	4.800
dma<9>.Q	dma<0>.D	4.800
dma<9>.Q	dma<1>.D	4.800
dma<9>.Q	dma<2>.D	4.800
dma<9>.Q	dma<3>.D	4.800
dma<9>.Q	dma<4>.D	4.800
dma<9>.Q	dma<5>.D	4.800
dma<9>.Q	dma<6>.D	4.800
dma<9>.Q	dma<7>.D	4.800
dma<9>.Q	dma<8>.D	4.800
per.Q	per.D	4.800
wls.Q	wls.D	4.800
writing.Q	per.D	4.800
writing.Q	wls.D	4.800
writing.Q	writing.D	4.800

Pad to Pad List

Source Pad	Destination Pad	Delay
md_L<10>	int_rq_L	15.500
md_L<11>	int_rq_L	15.500
md_L<3>	int_rq_L	15.500
md_L<4>	int_rq_L	15.500
md_L<5>	int_rq_L	15.500
md_L<6>	int_rq_L	15.500
md_L<7>	int_rq_L	15.500
md_L<8>	int_rq_L	15.500
md_L<9>	int_rq_L	15.500
tp3	int_rq_L	15.200
data_L<3>	int_rq_L	14.900
data_L<4>	int_rq_L	14.900
data_L<5>	int_rq_L	14.900
md_L<11>	data_L<7>	11.400
md_L<3>	data_L<7>	11.400
md_L<4>	data_L<7>	11.400
md_L<5>	data_L<7>	11.400
md_L<6>	data_L<7>	11.400
md_L<7>	data_L<7>	11.400
md_L<8>	data_L<7>	11.400
md_L<9>	data_L<7>	11.400
pca_L	int_rq_L	11.400
ts4_L	data_L<7>	11.400
word_L	data_L<7>	11.400
md_L<10>	data_L<7>	11.200
md_L<10>	data_L<4>	10.900
md_L<10>	data_L<5>	10.900
md_L<10>	data_L<6>	10.900
md_L<10>	data_L<8>	10.900
md_L<11>	data_L<4>	10.900
md_L<11>	data_L<5>	10.900
md_L<11>	data_L<6>	10.900
md_L<11>	data_L<8>	10.900
md_L<3>	data_L<4>	10.900
md_L<3>	data_L<5>	10.900
md_L<3>	data_L<6>	10.900
md_L<3>	data_L<8>	10.900
md_L<4>	data_L<4>	10.900
md_L<4>	data_L<5>	10.900
md_L<4>	data_L<6>	10.900
md_L<4>	data_L<8>	10.900
md_L<5>	data_L<4>	10.900
md_L<5>	data_L<5>	10.900
md_L<5>	data_L<6>	10.900
md_L<5>	data_L<8>	10.900
md_L<6>	data_L<4>	10.900
md_L<6>	data_L<5>	10.900
md_L<6>	data_L<6>	10.900
md_L<6>	data_L<8>	10.900
md_L<7>	data_L<4>	10.900
md_L<7>	data_L<5>	10.900
md_L<7>	data_L<6>	10.900
md_L<7>	data_L<8>	10.900
md_L<8>	data_L<4>	10.900
md_L<8>	data_L<5>	10.900
md_L<8>	data_L<6>	10.900
md_L<8>	data_L<8>	10.900
md_L<9>	data_L<4>	10.900
md_L<9>	data_L<5>	10.900
md_L<9>	data_L<6>	10.900
md_L<9>	data_L<8>	10.900
tp3	data_L<7>	10.900
tp3	data_L<4>	10.600
tp3	data_L<5>	10.600
tp3	data_L<6>	10.600
tp3	data_L<8>	10.600
md_L<10>	data_L<3>	10.100
md_L<11>	data_L<3>	10.100
md_L<3>	data_L<3>	10.100
md_L<4>	data_L<3>	10.100
md_L<5>	data_L<3>	10.100
md_L<6>	data_L<3>	10.100
md_L<7>	data_L<3>	10.100
md_L<8>	data_L<3>	10.100
md_L<9>	data_L<3>	10.100
tp3	data_L<3>	9.800
md_L<11>	data_L<0>	8.400
md_L<11>	data_L<10>	8.400
md_L<11>	data_L<11>	8.400
md_L<11>	data_L<1>	8.400
md_L<11>	data_L<2>	8.400
md_L<11>	data_L<9>	8.400
md_L<3>	data_L<0>	8.400
md_L<3>	data_L<10>	8.400
md_L<3>	data_L<11>	8.400
md_L<3>	data_L<1>	8.400
md_L<3>	data_L<2>	8.400
md_L<3>	data_L<9>	8.400
md_L<4>	data_L<0>	8.400
md_L<4>	data_L<10>	8.400
md_L<4>	data_L<11>	8.400
md_L<4>	data_L<1>	8.400
md_L<4>	data_L<2>	8.400
md_L<4>	data_L<9>	8.400
md_L<5>	data_L<0>	8.400
md_L<5>	data_L<10>	8.400
md_L<5>	data_L<11>	8.400
md_L<5>	data_L<1>	8.400
md_L<5>	data_L<2>	8.400
md_L<5>	data_L<9>	8.400
md_L<6>	data_L<0>	8.400
md_L<6>	data_L<10>	8.400
md_L<6>	data_L<11>	8.400
md_L<6>	data_L<1>	8.400
md_L<6>	data_L<2>	8.400
md_L<6>	data_L<9>	8.400
md_L<7>	data_L<0>	8.400
md_L<7>	data_L<10>	8.400
md_L<7>	data_L<11>	8.400
md_L<7>	data_L<1>	8.400
md_L<7>	data_L<2>	8.400
md_L<7>	data_L<9>	8.400
md_L<8>	data_L<0>	8.400
md_L<8>	data_L<10>	8.400
md_L<8>	data_L<11>	8.400
md_L<8>	data_L<1>	8.400
md_L<8>	data_L<2>	8.400
md_L<8>	data_L<9>	8.400
md_L<9>	data_L<0>	8.400
md_L<9>	data_L<10>	8.400
md_L<9>	data_L<11>	8.400
md_L<9>	data_L<1>	8.400
md_L<9>	data_L<2>	8.400
md_L<9>	data_L<9>	8.400
md_L<10>	c0_L	7.100
md_L<11>	c0_L	7.100
md_L<3>	c0_L	7.100
md_L<4>	c0_L	7.100
md_L<5>	c0_L	7.100
md_L<6>	c0_L	7.100
md_L<7>	c0_L	7.100
md_L<8>	c0_L	7.100
md_L<9>	c0_L	7.100
md_L<10>	data_L<0>	6.800
md_L<10>	data_L<10>	6.800
md_L<10>	data_L<11>	6.800
md_L<10>	data_L<1>	6.800
md_L<10>	data_L<2>	6.800
md_L<10>	skip_L	6.800
md_L<11>	skip_L	6.800
md_L<3>	skip_L	6.800
md_L<4>	skip_L	6.800
md_L<5>	skip_L	6.800
md_L<6>	skip_L	6.800
md_L<7>	skip_L	6.800
md_L<8>	skip_L	6.800
pca_L	data_L<0>	6.800
md_L<0>	data_L<0>	6.000
md_L<10>	data_L<9>	6.000
md_L<11>	c1_L	6.000
md_L<1>	data_L<1>	6.000
md_L<2>	data_L<2>	6.000
md_L<3>	c1_L	6.000
md_L<4>	c1_L	6.000
md_L<5>	c1_L	6.000
md_L<6>	c1_L	6.000
md_L<7>	c1_L	6.000
md_L<8>	c1_L	6.000
md_L<9>	c1_L	6.000
md_L<9>	skip_L	6.000
protect	we_L	6.000

Number of paths analyzed: 1240
Number of Timing errors: 1240
Analysis Completed: Fri Apr 18 19:37:25 2014