Release 7.1i - xst H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s --> Reading design: rf08.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "rf08.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "rf08" Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : rf08 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : rf08.lso verilog2001 : YES safe_implementation : No Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "rfomni.v" Module compiled No errors in compilation Analysis of file <"rf08.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . WARNING:Xst:905 - "rfomni.v" line 212: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "rfomni.v". WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1779 - Inout is used but is never assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal
is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2111 - Clock of counter seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. WARNING:Xst:2110 - Clock of register seems to be also used in the data or control logic of that element. Found 1-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 12-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 20-bit subtractor for signal <$AUX_1>. Found 12-bit tristate buffer for signal . Found 8-bit down counter for signal . Found 12-bit down counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 93 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... failed to translate terminal to FCT ema_L[0] = If $n0010 Then 1 If !($n0010) Then - --> Total memory usage is 128632 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 34 ( 0 filtered) Number of infos : 1 ( 0 filtered)