// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: cpol_use 
// e1: sn7401 
// n_t_3x = !(n_t_2x & n_t_1x); 
// n_t_9x = !(n_t_14x & n_t_15x); 
// n_t_16x = !(n_t_23x & n_t_22x); 
// n_t_21x = !(n_t_28x & n_t_29x); 
// open collector 'wire-or's 
module m044b (n15v, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_27x, n_t_28x, n_t_29x, n_t_2x, n_t_3x, n_t_7x, n_t_8x, n_t_9x);
output n15v;
output n_t_13x;
input n_t_14x;
input n_t_15x;
output n_t_16x;
input n_t_1x;
output n_t_20x;
output n_t_21x;
input n_t_22x;
input n_t_23x;
output n_t_27x;
input n_t_28x;
input n_t_29x;
input n_t_2x;
output n_t_3x;
output n_t_7x;
output n_t_8x;
output n_t_9x;


assign n_t_16x = (n_t_23x & n_t_22x)? 1'b0: 1'bz;
assign n_t_21x = (n_t_28x & n_t_29x)? 1'b0: 1'bz;
assign n_t_3x = (n_t_2x & n_t_1x)? 1'b0: 1'bz;
assign n_t_9x = (n_t_14x & n_t_15x)? 1'b0: 1'bz;
endmodule