~/Verilog/bin/topld.pl M101A
info: 1n3606 ne 1n4148do35_10
warning: making d1/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d10/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d11/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d12/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d13/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d14/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d15/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d2/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d3/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d4/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d5/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d6/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d7/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d8/1n3606/ a connector
info: 1n3606 ne 1n4148do35_10
warning: making d9/1n3606/ a connector
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: 7400n ne dil14
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M101A.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M101AX.PLD || (rm M101AX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M101AX.PLD >vv || (rm vv; exit 1)
mv vv M101A.v
rm M101AX.PLD