// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// e1: sn7430 
module m103b (a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, n1, n2, n3v3, n_t_2x, p2, r2, s2, u2, v2);
output a1;
inout b1;
output c1;
inout d1;
input d2;
output e1;
input e2;
inout f1;
input f2;
input h1;
input h2;
input j1;
input j2;
output k1;
input k2;
input l1;
input l2;
input m1;
output n1;
input n2;
input n3v3;
output n_t_2x;
input p2;
input r2;
input s2;
input u2;
input v2;


wire n_t_8x;
wire n_t_9x;
assign n_t_8x = ~(f2 & h2 & j2 & k2 & l2 & n2 & d2 & e2);
// e2: sn74h40 
assign f1 = ~(n3v3 & v2 & s2);
assign e1 = ~(n3v3 & f1);
// e3: sn74h40 
assign d1 = ~(n3v3 & v2 & r2);
assign c1 = ~(n3v3 & d1);
// e4: sn7400 
assign n_t_2x = ~n_t_9x;
assign n1 = ~(l1 & m1);
assign n_t_9x = ~(u2 & n_t_8x);
assign k1 = ~(h1 & j1);
// e5: sn74h40 
assign b1 = ~(n3v3 & v2 & p2);
assign a1 = ~(n3v3 & b1);
// open collector 'wire-or's 
endmodule