// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: cpol_use 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// e1: sn7474 
module m104d (n3v3, n_t_8x, clr_flag_l, en_in, en_out, flag, grant, io_sync, k2, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_1x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, pwr_clr);
input n3v3;
input n_t_8x;
input clr_flag_l;
input en_in;
output en_out;
input flag;
input grant;
input io_sync;
output k2;
output n_t_10x;
input n_t_11x;
inout n_t_12x;
output n_t_13x;
inout reg n_t_14x;
inout reg n_t_15x;
inout reg n_t_16x;
inout n_t_1x;
inout reg n_t_2x;
inout n_t_3x;
input n_t_4x;
output n_t_5x;
input pwr_clr;

reg n_t_14x_m;
reg n_t_15x_m;
reg n_t_16x_m;
reg n_t_2x_m;

wire n_t_6x;
wire pwr_clr_l;
always @(io_sync, n_t_1x, pwr_clr_l, n_t_11x)
  if (~n_t_1x) begin
    n_t_15x_m <= 1'b0;
  end else
  if (~pwr_clr_l) begin
    n_t_15x_m <= 1'b1;
  end else
  if (~(io_sync)) begin
    n_t_15x_m <= n_t_11x;
  end
always @(io_sync, n_t_1x, pwr_clr_l, n_t_15x_m)
  if (~n_t_1x) begin
    n_t_15x <= 1'b0;
  end else
  if (~pwr_clr_l) begin
    n_t_15x <= 1'b1;
  end else
  if (io_sync) begin
    n_t_15x <= n_t_15x_m;
  end
assign n_t_12x = ~n_t_15x;
always @(io_sync, n3v3, n3v3, n_t_12x)
  if (~n3v3) begin
    n_t_14x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_14x_m <= 1'b1;
  end else
  if (~(io_sync)) begin
    n_t_14x_m <= n_t_12x;
  end
always @(io_sync, n3v3, n3v3, n_t_14x_m)
  if (~n3v3) begin
    n_t_14x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_14x <= 1'b1;
  end else
  if (io_sync) begin
    n_t_14x <= n_t_14x_m;
  end
assign n_t_13x = ~n_t_14x;
// e2: sn7400 
assign pwr_clr_l = ~(n3v3 & pwr_clr);
assign n_t_10x = ~(grant & n_t_12x);
// e3: sn74h40 
assign n_t_5x = ~(n3v3 & n_t_3x & en_in);
assign n_t_6x = ~(en_in & clr_flag_l & pwr_clr_l & n3v3);
// e4: sn7474 
always @(grant, n_t_8x, n3v3, n_t_4x)
  if (n_t_8x) begin
    n_t_16x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_16x_m <= 1'b1;
  end else
  if (~(grant)) begin
    n_t_16x_m <= n_t_4x;
  end
always @(grant, n_t_8x, n3v3, n_t_16x_m)
  if (n_t_8x) begin
    n_t_16x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_16x <= 1'b1;
  end else
  if (grant) begin
    n_t_16x <= n_t_16x_m;
  end
assign n_t_1x = ~n_t_16x;
always @(io_sync, n_t_6x, n3v3, flag)
  if (n_t_6x) begin
    n_t_2x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_2x_m <= 1'b1;
  end else
  if (~(io_sync)) begin
    n_t_2x_m <= flag;
  end
always @(io_sync, n_t_6x, n3v3, n_t_2x_m)
  if (n_t_6x) begin
    n_t_2x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_2x <= 1'b1;
  end else
  if (io_sync) begin
    n_t_2x <= n_t_2x_m;
  end
assign n_t_3x = ~n_t_2x;
// open collector 'wire-or's 
endmodule