// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: cpol_use 
// e1: sp380n 
module m105c (n_t_21x, n_t_31x, n_t_32x, n_t_33x, n_t_34x, n_t_35x, n_t_36x, n_t_37x, n_t_39x, n_t_40x, n_t_48x, c1_l, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_22x, n_t_23x, n_t_24x, n_t_2x, n_t_3x, n_t_43x, n_t_44x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x, out_high, out_l, select0, select2, select4, select6, ssyn_l, testpoint);
input n_t_21x;
input n_t_31x;
input n_t_32x;
input n_t_33x;
input n_t_34x;
input n_t_35x;
input n_t_36x;
input n_t_37x;
input n_t_39x;
input n_t_40x;
input n_t_48x;
inout c1_l;
input n_t_10x;
input n_t_11x;
input n_t_12x;
input n_t_13x;
input n_t_14x;
input n_t_15x;
input n_t_16x;
input n_t_17x;
input n_t_18x;
input n_t_19x;
input n_t_1x;
output n_t_20x;
output n_t_22x;
input n_t_23x;
input n_t_24x;
input n_t_2x;
input n_t_3x;
inout n_t_43x;
input n_t_44x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;
input n_t_9x;
output out_high;
output out_l;
output select0;
output select2;
output select4;
output select6;
output ssyn_l;
inout testpoint;


wire a00;
wire a01;
wire a02;
wire a03;
wire a04;
wire a05;
wire a06;
wire a07;
wire a08;
wire a09;
wire a10;
wire a11;
wire a12;
wire a1314;
wire a1516;
wire a17syn;
wire c0;
wire c1;
wire n_t_38x;
wire n_t_41x;
assign a00 = ~n_t_18x;
assign a01 = ~n_t_19x;
assign a02 = ~n_t_17x;
// e2: sp380n 
assign a1314 = ~(n_t_5x
                  | n_t_6x);
assign c0 = ~n_t_23x;
assign a17syn = ~(n_t_2x
                   | n_t_1x);
assign a1516 = ~(n_t_3x
                  | n_t_4x);
// e3: sp380n 
assign a11 = ~n_t_8x;
assign c1 = ~n_t_24x;
assign a12 = ~n_t_7x;
// e4: dec8242 
// n_t_43x = !(!n_t_31x & !a11
//        # n_t_31x & a11); 
// n_t_43x = !(!n_t_32x & !a1314
//        # n_t_32x & a1314); 
// n_t_43x = !(!a1516 & !n_t_32x
//        # a1516 & n_t_32x); 
// n_t_43x = !(!a12 & !n_t_21x
//        # a12 & n_t_21x); 
// e5: sn74h00 
assign testpoint = ~(n_t_43x & a17syn);
assign c1_l = ~c1;
// e6: sn7402 
assign out_l = ~(n_t_38x
                  | c1_l);
assign out_high = ~(c1_l
                     | n_t_41x);
assign n_t_41x = ~(a00
                    | ~c0);
assign n_t_38x = ~(~a00
                    | ~c0);
// e7: sp380n 
assign a07 = ~n_t_12x;
assign a08 = ~n_t_10x;
assign a10 = ~n_t_9x;
assign a09 = ~n_t_11x;
// e8: dec8242 
// n_t_43x = !(!n_t_48x & !a07
//        # n_t_48x & a07); 
// n_t_43x = !(!a08 & !n_t_37x
//        # a08 & n_t_37x); 
// n_t_43x = !(!a10 & !n_t_40x
//        # a10 & n_t_40x); 
// n_t_43x = !(!a09 & !n_t_39x
//        # a09 & n_t_39x); 
// e9: n8815 
assign select6 = ~(~a02
                    | testpoint
                    | ~a01);
assign select4 = ~(testpoint
                    | a01
                    | ~a02
                    | ~a02);
// e10: n8815 
assign select2 = ~(testpoint
                    | ~a01
                    | ~a01
                    | a02);
assign select0 = ~(a02
                    | a01
                    | a01
                    | testpoint);
// e11: sp380n 
assign a03 = ~n_t_16x;
assign a04 = ~n_t_15x;
assign a06 = ~n_t_13x;
assign a05 = ~n_t_14x;
// e12: dec8242 
// n_t_43x = !(!n_t_33x & !a03
//        # n_t_33x & a03); 
// n_t_43x = !(!a04 & !n_t_34x
//        # a04 & n_t_34x); 
// n_t_43x = !(!a06 & !n_t_36x
//        # a06 & n_t_36x); 
// n_t_43x = !(!a05 & !n_t_35x
//        # a05 & n_t_35x); 
// e13: n8881n 
// n_t_22x = !testpoint; 
// ssyn_l = !n_t_44x; 
// open collector 'wire-or's 
assign n_t_22x = testpoint? ~testpoint: 1'bz;
assign n_t_43x = (~n_t_31x & ~a11
                   | n_t_31x & a11)
                  | (~n_t_32x & ~a1314
                     | n_t_32x & a1314)
                  | (~a1516 & ~n_t_32x
                     | a1516 & n_t_32x)
                  | (~a12 & ~n_t_21x
                     | a12 & n_t_21x)
                  | (~n_t_48x & ~a07
                     | n_t_48x & a07)
                  | (~a08 & ~n_t_37x
                     | a08 & n_t_37x)
                  | (~a10 & ~n_t_40x
                     | a10 & n_t_40x)
                  | (~a09 & ~n_t_39x
                     | a09 & n_t_39x)
                  | (~n_t_33x & ~a03
                     | n_t_33x & a03)
                  | (~a04 & ~n_t_34x
                     | a04 & n_t_34x)
                  | (~a06 & ~n_t_36x
                     | a06 & n_t_36x)
                  | (~a05 & ~n_t_35x
                     | a05 & n_t_35x)? 1'b0: 1'bz;
assign ssyn_l = n_t_44x? ~n_t_44x: 1'bz;
endmodule