~/Verilog/bin/topld.pl M1091A
info: cpol_use ne cpol_use20_8axial
info: sp380n ne dil14
info: sp380n ne dil14
info: sp380n ne dil14
info: sp380n ne dil14
info: sp380n ne dil14
info: 74h04n ne 7404n
info: 74h30n ne 7430n
info: 74h04n ne 7404n
info: 0r ne 0r/10
warning: making j1/0r/ a connector
info: 0r ne 0r/10
warning: making j10/0r/ a connector
info: 0r ne 0r/10
warning: making j11/0r/ a connector
info: 0r ne 0r/10
warning: making j12/0r/ a connector
info: 0r ne 0r/10
warning: making j13/0r/ a connector
info: 0r ne 0r/10
warning: making j14/0r/ a connector
info: 0r ne 0r/10
warning: making j15/0r/ a connector
info: 0r ne 0r/10
warning: making j16/0r/ a connector
info: 0r ne 0r/10
warning: making j17/0r/ a connector
info: 0r ne 0r/10
warning: making j18/0r/ a connector
info: 0r ne 0r/10
warning: making j19/0r/ a connector
info: 0r ne 0r/10
warning: making j2/0r/ a connector
info: 0r ne 0r/10
warning: making j3/0r/ a connector
info: 0r ne 0r/10
warning: making j4/0r/ a connector
info: 0r ne 0r/10
warning: making j5/0r/ a connector
info: 0r ne 0r/10
warning: making j6/0r/ a connector
info: 0r ne 0r/10
warning: making j7/0r/ a connector
info: 0r ne 0r/10
warning: making j8/0r/ a connector
info: 0r ne 0r/10
warning: making j9/0r/ a connector
info: single ne edge_con2
warning: making u$2/single/ a connector
~/Verilog/bin/smaller.pl M1091A.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M1091AX.PLD || (rm M1091AX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M1091AX.PLD >vv || (rm vv; exit 1)
mv vv M1091A.v
rm M1091AX.PLD