// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: cpol_use 
// e1: sp380n 
module m1091x (n_t_101x, n_t_10x, n_t_136x, n_t_2x, n_t_77x, n_t_91x, n_t_96x, n_t_98x, a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, n_t_17x, n_t_18x, n_t_45x, n_t_46x, n_t_47x, n_t_4x, n_t_56x, n_t_57x, n_t_59x, n_t_68x, n_t_76x, n_t_78x, n_t_82x, n_t_84x, n_t_86x, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input n_t_101x;
input n_t_10x;
input n_t_136x;
input n_t_2x;
input n_t_77x;
input n_t_91x;
input n_t_96x;
input n_t_98x;
output a1;
output b1;
input c1;
input d1;
input d2;
input e1;
output e2;
output f1;
input f2;
output h1;
input h2;
input j1;
output j2;
input k1;
output k2;
output l1;
input l2;
output m1;
input m2;
input n1;
output n2;
output n_t_17x;
inout n_t_18x;
output n_t_45x;
inout n_t_46x;
output n_t_47x;
inout n_t_4x;
inout n_t_56x;
inout n_t_57x;
inout n_t_59x;
output n_t_68x;
output n_t_76x;
output n_t_78x;
output n_t_82x;
output n_t_84x;
output n_t_86x;
output p1;
input p2;
input r1;
output r2;
input s1;
output s2;
input t2;
input u1;
input u2;
input v1;
input v2;


assign j2 = ~l2;
assign a1 = ~d1;
assign b1 = ~c1;
// e2: sp380n 
assign k2 = ~k1;
assign n2 = ~p2;
assign f1 = ~h2;
assign h1 = ~j1;
// e3: sp380n 
assign r2 = ~s1;
assign p1 = ~r1;
assign l1 = ~m2;
assign m1 = ~n1;
// e4: sp380n 
assign n_t_47x = ~v2;
assign n_t_46x = ~f2;
assign n_t_45x = ~e1;
// e5: sp380n 
assign n_t_56x = ~v1;
assign n_t_59x = ~u1;
assign n_t_18x = ~t2;
assign n_t_57x = ~u2;
// e6: sn74h04 
assign s2 = ~n_t_4x;
assign n_t_76x = ~d2;
assign n_t_68x = ~n_t_46x;
assign n_t_78x = ~n_t_77x;
// e7: sn74h30 
assign n_t_4x = ~(n_t_10x & n_t_101x & n_t_136x & n_t_96x & n_t_96x & n_t_98x & n_t_91x & n_t_2x);
// e8: sn74h04 
assign n_t_82x = ~n_t_57x;
assign n_t_84x = ~n_t_59x;
assign n_t_86x = ~n_t_56x;
assign n_t_17x = ~n_t_18x;
// open collector 'wire-or's 
endmodule