// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// e1: sn7402 
module m112d (a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input a1;
input b1;
output c1;
input d1;
input d2;
input e1;
input e2;
output f1;
output f2;
input h1;
input h2;
input j1;
input j2;
output k1;
output k2;
input l1;
input l2;
input m1;
input m2;
output n1;
output n2;
input p1;
input p2;
input r1;
input r2;
output s1;
output s2;
input t2;
output u1;
input u2;
output v1;
output v2;


assign k1 = ~(j1
               | h1);
assign f1 = ~(d1
               | e1);
assign f2 = ~(e2
               | d2);
assign c1 = ~(b1
               | a1);
// e2: sn7402 
assign k2 = ~(j2
               | h2);
assign n1 = ~(m1
               | l1);
// e3: sn7402 
assign v2 = ~(u2
               | t2);
assign s2 = ~(r2
               | p2);
assign n2 = ~(m2
               | l2);
assign s1 = ~(r1
               | p1);
// open collector 'wire-or's 
endmodule