~/Verilog/bin/topld.pl M117E
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M117E.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M117EX.PLD || (rm M117EX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M117EX.PLD >vv || (rm vv; exit 1)
mv vv M117E.v
rm M117EX.PLD