// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: cpol_use 
// e1: sn7474 
module m1501b (b, d, dd, f, ff, j, jj, l, ll, n, nn, r, rr, t, tt, vv, a1, b1, bb, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, n3v3, p1, p2, r1, r2, s1, s2, t2, u2, x, z);
input b;
input d;
input dd;
input f;
input ff;
input j;
input jj;
input l;
input ll;
input n;
input nn;
input r;
input rr;
input t;
input tt;
input vv;
output a1;
input b1;
output bb;
input c1;
output d1;
input d2;
input e1;
input e2;
input f1;
input f2;
input h1;
input h2;
output j1;
input j2;
output k1;
input k2;
output l1;
output l2;
output m1;
output m2;
output n1;
output n2;
input n3v3;
output p1;
output p2;
output r1;
output r2;
output s1;
output s2;
output t2;
output u2;
output x;
output z;

reg n_t_164x_m;
reg n_t_71x_m;

reg n_t_71x;
reg n_t_164x;
wire n_t_154x;
wire n_t_158x;
wire n_t_1x;
wire n_t_69x;
always @(n_t_69x, n_t_158x, n3v3, e1)
  if (~n_t_158x) begin
    n_t_71x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_71x_m <= 1'b1;
  end else
  if (~(n_t_69x)) begin
    n_t_71x_m <= ~e1;
  end
always @(n_t_69x, n_t_158x, n3v3, n_t_71x_m)
  if (~n_t_158x) begin
    n_t_71x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_71x <= 1'b1;
  end else
  if (n_t_69x) begin
    n_t_71x <= n_t_71x_m;
  end
assign d1 = ~(~n_t_71x);
always @(d2, b1, n_t_154x, h1)
  if (b1) begin
    n_t_164x_m <= 1'b0;
  end else
  if (~n_t_154x) begin
    n_t_164x_m <= 1'b1;
  end else
  if (~(d2)) begin
    n_t_164x_m <= h1;
  end
always @(d2, b1, n_t_154x, n_t_164x_m)
  if (b1) begin
    n_t_164x <= 1'b0;
  end else
  if (~n_t_154x) begin
    n_t_164x <= 1'b1;
  end else
  if (d2) begin
    n_t_164x <= n_t_164x_m;
  end
// e2: sn7437 
assign bb = ~n_t_71x;
assign a1 = ~n_t_164x;
// e3: n8881n 
// k1 = !(ll & !n_t_1x); 
// j1 = !(jj & !n_t_1x); 
// l2 = !(!n_t_1x & ff); 
// m2 = !(dd & !n_t_1x); 
// e4: sn7402 
assign n_t_158x = ~(e2
                     | ~f1);
assign n_t_154x = ~(~f1
                     | c1);
// e5: ds8640n 
// e6: n8881n 
// m1 = !(rr & !n_t_1x); 
// l1 = !(nn & !n_t_1x); 
// n2 = !(!n_t_1x & tt); 
// p2 = !(!n_t_1x & vv); 
// e7: sn7400 
assign n_t_1x = ~(k2 & j2);
assign n_t_69x = ~(f2 & ~h2);
// e8: n8881n 
// p1 = !(b & !n_t_1x); 
// n1 = !(d & !n_t_1x); 
// r2 = !(!n_t_1x & f); 
// s2 = !(!n_t_1x & j); 
// e9: n8881n 
// s1 = !(t & !n_t_1x); 
// r1 = !(r & !n_t_1x); 
// t2 = !(!n_t_1x & l); 
// u2 = !(!n_t_1x & n); 
// open collector 'wire-or's 
assign j1 = (jj & ~n_t_1x)? 1'b0: 1'bz;
assign k1 = (ll & ~n_t_1x)? 1'b0: 1'bz;
assign l1 = (nn & ~n_t_1x)? 1'b0: 1'bz;
assign l2 = (~n_t_1x & ff)? 1'b0: 1'bz;
assign m1 = (rr & ~n_t_1x)? 1'b0: 1'bz;
assign m2 = (dd & ~n_t_1x)? 1'b0: 1'bz;
assign n1 = (d & ~n_t_1x)? 1'b0: 1'bz;
assign n2 = (~n_t_1x & tt)? 1'b0: 1'bz;
assign p1 = (b & ~n_t_1x)? 1'b0: 1'bz;
assign p2 = (~n_t_1x & vv)? 1'b0: 1'bz;
assign r1 = (r & ~n_t_1x)? 1'b0: 1'bz;
assign r2 = (~n_t_1x & f)? 1'b0: 1'bz;
assign s1 = (t & ~n_t_1x)? 1'b0: 1'bz;
assign s2 = (~n_t_1x & j)? 1'b0: 1'bz;
assign t2 = (~n_t_1x & l)? 1'b0: 1'bz;
assign u2 = (~n_t_1x & n)? 1'b0: 1'bz;
endmodule