// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: cpol_use 
// c25: c_us 
// e1: sn7400 
module m1502c (aa1, ab1, ac1, ad1, ad2, ae1, ae2, af1, af2, ah1, ah2, aj1, aj2, ak1, ak2, al2, am1, am2, an1, an2, ap1, ap2, ar1, as1, as2, at2, au2, av1, av2, b, ba1, bb, bb1, bc1, bd1, bd2, be1, be2, bf1, bf2, bh1, bh2, bj1, bj2, bk1, bk2, bl1, bl2, bm1, bm2, bn1, bn2, bp1, bp2, br1, br2, bs1, bs2, bt2, bu1, bu2, bv1, bv2, d, dd, f, ff, j, jj, l, ll, n, n3v3, nn, r, rr, t, tt, v, vv, x, z);
input aa1;
input ab1;
input ac1;
input ad1;
input ad2;
input ae1;
input ae2;
input af1;
input af2;
input ah1;
input ah2;
input aj1;
input aj2;
input ak1;
input ak2;
output al2;
input am1;
input am2;
output an1;
input an2;
input ap1;
output ap2;
input ar1;
output as1;
input as2;
input at2;
input au2;
output av1;
output av2;
output b;
output ba1;
output bb;
input bb1;
input bc1;
input bd1;
input bd2;
input be1;
input be2;
input bf1;
input bf2;
input bh1;
input bh2;
input bj1;
input bj2;
input bk1;
output bk2;
output bl1;
output bl2;
output bm1;
output bm2;
output bn1;
output bn2;
output bp1;
output bp2;
output br1;
output br2;
output bs1;
output bs2;
input bt2;
output bu1;
output bu2;
input bv1;
output bv2;
output d;
output dd;
output f;
output ff;
output j;
output jj;
output l;
output ll;
output n;
input n3v3;
output nn;
output r;
output rr;
output t;
output tt;
output v;
output vv;
output x;
output z;

reg n_t_100x_m;
reg n_t_102x_m;
reg n_t_108x_m;
reg n_t_109x_m;
reg n_t_110x_m;
reg n_t_111x_m;
reg n_t_112x_m;
reg n_t_113x_m;
reg n_t_120x_m;
reg n_t_121x_m;
reg n_t_122x_m;
reg n_t_123x_m;
reg n_t_124x_m;
reg n_t_125x_m;
reg n_t_56x_m;
reg n_t_89x_m;
reg n_t_90x_m;
reg n_t_98x_m;
reg n_t_99x_m;

reg n_t_56x;
reg n_t_89x;
reg n_t_90x;
reg n_t_109x;
reg n_t_111x;
reg n_t_108x;
reg n_t_112x;
reg n_t_124x;
reg n_t_120x;
reg n_t_123x;
reg n_t_121x;
reg n_t_102x;
reg n_t_98x;
reg n_t_110x;
reg n_t_113x;
reg n_t_100x;
reg n_t_99x;
reg n_t_122x;
reg n_t_125x;
wire an1_l;
wire an1clk;
wire an1clr_l;
wire as1clr_l;
wire ba1_l;
wire ba1clk;
wire ba1clr_l;
wire bk2_l;
wire bl1_l;
wire bl2_l;
wire bm1_l;
wire bm2_l;
wire bn1_l;
wire bn2_l;
wire bp1_l;
wire bp2_l;
wire br1_l;
wire br2_l;
wire bs1_l;
wire bs2_l;
wire bu1_l;
wire bu2_l;
wire bv2_l;
wire dataclr_l;
wire hclk;
wire lclk;
assign an1clk = ~(~af1 & ah1);
assign ba1clk = ~(~ae2 & ad2);
// e2: ds8640n 
// e3: sn7402 
assign dataclr_l = ~(ap1
                      | ~ae1);
assign an1clr_l = ~(~ae1
                     | ar1);
assign as1clr_l = ~(~ae1
                     | ah2);
assign ba1clr_l = ~(~ae1
                     | af2);
// e4: sn7474 
always @(bj2, as1clr_l, aj1)
  if (~as1clr_l) begin
    n_t_56x_m <= 1'b1;
  end else
  if (~(bj2)) begin
    n_t_56x_m <= aj1;
  end
always @(bj2, as1clr_l, n_t_56x_m)
  if (~as1clr_l) begin
    n_t_56x <= 1'b1;
  end else
  if (bj2) begin
    n_t_56x <= n_t_56x_m;
  end
// e5: sn7402 
assign lclk = ~(~aa1
                 | ~am1);
assign hclk = ~(~ab1
                 | ~am1);
// e6: sn7400 
// e7: sn7437 
assign an1 = ~an1_l;
assign ba1 = ~ba1_l;
assign as1 = ~n_t_56x;
// e8: sn7474 
always @(ba1clk, ba1clr_l, n3v3, aj2)
  if (~ba1clr_l) begin
    n_t_89x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_89x_m <= 1'b1;
  end else
  if (~(ba1clk)) begin
    n_t_89x_m <= ~aj2;
  end
always @(ba1clk, ba1clr_l, n3v3, n_t_89x_m)
  if (~ba1clr_l) begin
    n_t_89x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_89x <= 1'b1;
  end else
  if (ba1clk) begin
    n_t_89x <= n_t_89x_m;
  end
assign ba1_l = ~n_t_89x;
always @(an1clk, an1clr_l, n3v3, ak1)
  if (~an1clr_l) begin
    n_t_90x_m <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_90x_m <= 1'b1;
  end else
  if (~(an1clk)) begin
    n_t_90x_m <= ~ak1;
  end
always @(an1clk, an1clr_l, n3v3, n_t_90x_m)
  if (~an1clr_l) begin
    n_t_90x <= 1'b0;
  end else
  if (~n3v3) begin
    n_t_90x <= 1'b1;
  end else
  if (an1clk) begin
    n_t_90x <= n_t_90x_m;
  end
assign an1_l = ~n_t_90x;
// e9: sn7406 
// v = !n_t_89x; 
// b = !n_t_100x; 
// j = !n_t_99x; 
// tt = !n_t_98x; 
// rr = !n_t_102x; 
// bb = !n_t_90x; 
// e10: n8881n 
// av2 = !(au2 & at2); 
// av1 = !(at2 & as2); 
// al2 = !(am2 & ak2); 
// ap2 = !(ak2 & an2); 
// e11: sn7406 
// jj = !n_t_108x; 
// ff = !n_t_112x; 
// dd = !n_t_111x; 
// nn = !n_t_110x; 
// ll = !n_t_113x; 
// vv = !n_t_109x; 
// e12: sn7406 
// l = !n_t_120x; 
// n = !n_t_124x; 
// t = !n_t_123x; 
// d = !n_t_122x; 
// f = !n_t_125x; 
// r = !n_t_121x; 
// e13: ds8640n 
// e14: ds8640n 
// e15: ds8640n 
// e16: ds8640n 
// e17: sn7404 
assign bn1 = ~bn1_l;
assign bv2 = ~bv2_l;
assign bu2 = ~bu2_l;
assign bp1 = ~bp1_l;
// e18: sn7404 
assign bl2 = ~bl2_l;
assign bm2 = ~bm2_l;
assign bn2 = ~bn2_l;
assign bk2 = ~bk2_l;
assign bl1 = ~bl1_l;
assign bm1 = ~bm1_l;
// e19: sn74175 
always @(lclk, dataclr_l, be1)
  if (~dataclr_l) begin
    n_t_109x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_109x_m <= ~be1;
  end
always @(lclk, dataclr_l, n_t_109x_m)
  if (~dataclr_l) begin
    n_t_109x <= 1'b0;
  end else
  if (lclk) begin
    n_t_109x <= n_t_109x_m;
  end
assign bu1_l = ~n_t_109x;
always @(lclk, dataclr_l, bd1)
  if (~dataclr_l) begin
    n_t_111x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_111x_m <= ~bd1;
  end
always @(lclk, dataclr_l, n_t_111x_m)
  if (~dataclr_l) begin
    n_t_111x <= 1'b0;
  end else
  if (lclk) begin
    n_t_111x <= n_t_111x_m;
  end
assign bl2_l = ~n_t_111x;
always @(lclk, dataclr_l, bf1)
  if (~dataclr_l) begin
    n_t_108x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_108x_m <= ~bf1;
  end
always @(lclk, dataclr_l, n_t_108x_m)
  if (~dataclr_l) begin
    n_t_108x <= 1'b0;
  end else
  if (lclk) begin
    n_t_108x <= n_t_108x_m;
  end
assign bm1_l = ~n_t_108x;
always @(lclk, dataclr_l, bh1)
  if (~dataclr_l) begin
    n_t_112x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_112x_m <= ~bh1;
  end
always @(lclk, dataclr_l, n_t_112x_m)
  if (~dataclr_l) begin
    n_t_112x <= 1'b0;
  end else
  if (lclk) begin
    n_t_112x <= n_t_112x_m;
  end
assign bl1_l = ~n_t_112x;
// e20: sn74175 
always @(hclk, dataclr_l, bc1)
  if (~dataclr_l) begin
    n_t_124x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_124x_m <= ~bc1;
  end
always @(hclk, dataclr_l, n_t_124x_m)
  if (~dataclr_l) begin
    n_t_124x <= 1'b0;
  end else
  if (hclk) begin
    n_t_124x <= n_t_124x_m;
  end
assign bv2_l = ~n_t_124x;
always @(hclk, dataclr_l, bb1)
  if (~dataclr_l) begin
    n_t_120x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_120x_m <= ~bb1;
  end
always @(hclk, dataclr_l, n_t_120x_m)
  if (~dataclr_l) begin
    n_t_120x <= 1'b0;
  end else
  if (hclk) begin
    n_t_120x <= n_t_120x_m;
  end
assign bn2_l = ~n_t_120x;
always @(hclk, dataclr_l, bk1)
  if (~dataclr_l) begin
    n_t_123x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_123x_m <= ~bk1;
  end
always @(hclk, dataclr_l, n_t_123x_m)
  if (~dataclr_l) begin
    n_t_123x <= 1'b0;
  end else
  if (hclk) begin
    n_t_123x <= n_t_123x_m;
  end
assign bk2_l = ~n_t_123x;
always @(hclk, dataclr_l, bj1)
  if (~dataclr_l) begin
    n_t_121x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_121x_m <= ~bj1;
  end
always @(hclk, dataclr_l, n_t_121x_m)
  if (~dataclr_l) begin
    n_t_121x <= 1'b0;
  end else
  if (hclk) begin
    n_t_121x <= n_t_121x_m;
  end
assign bu2_l = ~n_t_121x;
// e21: sn7404 
assign br2 = ~br2_l;
assign bs2 = ~bs2_l;
assign bu1 = ~bu1_l;
assign bp2 = ~bp2_l;
assign br1 = ~br1_l;
assign bs1 = ~bs1_l;
// e22: sn74175 
always @(lclk, dataclr_l, bh2)
  if (~dataclr_l) begin
    n_t_102x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_102x_m <= ~bh2;
  end
always @(lclk, dataclr_l, n_t_102x_m)
  if (~dataclr_l) begin
    n_t_102x <= 1'b0;
  end else
  if (lclk) begin
    n_t_102x <= n_t_102x_m;
  end
assign bs2_l = ~n_t_102x;
always @(lclk, dataclr_l, bf2)
  if (~dataclr_l) begin
    n_t_98x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_98x_m <= ~bf2;
  end
always @(lclk, dataclr_l, n_t_98x_m)
  if (~dataclr_l) begin
    n_t_98x <= 1'b0;
  end else
  if (lclk) begin
    n_t_98x <= n_t_98x_m;
  end
assign br2_l = ~n_t_98x;
always @(lclk, dataclr_l, bd2)
  if (~dataclr_l) begin
    n_t_110x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_110x_m <= ~bd2;
  end
always @(lclk, dataclr_l, n_t_110x_m)
  if (~dataclr_l) begin
    n_t_110x <= 1'b0;
  end else
  if (lclk) begin
    n_t_110x <= n_t_110x_m;
  end
assign bs1_l = ~n_t_110x;
always @(lclk, dataclr_l, be2)
  if (~dataclr_l) begin
    n_t_113x_m <= 1'b0;
  end else
  if (~(lclk)) begin
    n_t_113x_m <= ~be2;
  end
always @(lclk, dataclr_l, n_t_113x_m)
  if (~dataclr_l) begin
    n_t_113x <= 1'b0;
  end else
  if (lclk) begin
    n_t_113x <= n_t_113x_m;
  end
assign br1_l = ~n_t_113x;
// e23: sn74175 
always @(hclk, dataclr_l, bt2)
  if (~dataclr_l) begin
    n_t_100x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_100x_m <= ~bt2;
  end
always @(hclk, dataclr_l, n_t_100x_m)
  if (~dataclr_l) begin
    n_t_100x <= 1'b0;
  end else
  if (hclk) begin
    n_t_100x <= n_t_100x_m;
  end
assign bp1_l = ~n_t_100x;
always @(hclk, dataclr_l, bv1)
  if (~dataclr_l) begin
    n_t_99x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_99x_m <= ~bv1;
  end
always @(hclk, dataclr_l, n_t_99x_m)
  if (~dataclr_l) begin
    n_t_99x <= 1'b0;
  end else
  if (hclk) begin
    n_t_99x <= n_t_99x_m;
  end
assign bm2_l = ~n_t_99x;
always @(hclk, dataclr_l, ad1)
  if (~dataclr_l) begin
    n_t_122x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_122x_m <= ~ad1;
  end
always @(hclk, dataclr_l, n_t_122x_m)
  if (~dataclr_l) begin
    n_t_122x <= 1'b0;
  end else
  if (hclk) begin
    n_t_122x <= n_t_122x_m;
  end
assign bp2_l = ~n_t_122x;
always @(hclk, dataclr_l, ac1)
  if (~dataclr_l) begin
    n_t_125x_m <= 1'b0;
  end else
  if (~(hclk)) begin
    n_t_125x_m <= ~ac1;
  end
always @(hclk, dataclr_l, n_t_125x_m)
  if (~dataclr_l) begin
    n_t_125x <= 1'b0;
  end else
  if (hclk) begin
    n_t_125x <= n_t_125x_m;
  end
assign bn1_l = ~n_t_125x;
// open collector 'wire-or's 
assign al2 = (am2 & ak2)? 1'b0: 1'bz;
assign ap2 = (ak2 & an2)? 1'b0: 1'bz;
assign av1 = (at2 & as2)? 1'b0: 1'bz;
assign av2 = (au2 & at2)? 1'b0: 1'bz;
assign b = n_t_100x? ~n_t_100x: 1'bz;
assign bb = n_t_90x? ~n_t_90x: 1'bz;
assign d = n_t_122x? ~n_t_122x: 1'bz;
assign dd = n_t_111x? ~n_t_111x: 1'bz;
assign f = n_t_125x? ~n_t_125x: 1'bz;
assign ff = n_t_112x? ~n_t_112x: 1'bz;
assign j = n_t_99x? ~n_t_99x: 1'bz;
assign jj = n_t_108x? ~n_t_108x: 1'bz;
assign l = n_t_120x? ~n_t_120x: 1'bz;
assign ll = n_t_113x? ~n_t_113x: 1'bz;
assign n = n_t_124x? ~n_t_124x: 1'bz;
assign nn = n_t_110x? ~n_t_110x: 1'bz;
assign r = n_t_121x? ~n_t_121x: 1'bz;
assign rr = n_t_102x? ~n_t_102x: 1'bz;
assign t = n_t_123x? ~n_t_123x: 1'bz;
assign tt = n_t_98x? ~n_t_98x: 1'bz;
assign v = n_t_89x? ~n_t_89x: 1'bz;
assign vv = n_t_109x? ~n_t_109x: 1'bz;
endmodule