// this file is generated by topld.pl // please don't edit it. // input pins // output pins // internal nodes // code nodes // equations // c1: cpol_use // c2: c_us // c3: c_us // e1: sn74181 module m159x (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x); input n_t_10x; input n_t_11x; input n_t_12x; input n_t_13x; input n_t_14x; input n_t_15x; inout n_t_16x; output n_t_17x; output n_t_18x; output n_t_19x; input n_t_1x; inout n_t_20x; inout n_t_21x; inout n_t_22x; input n_t_2x; input n_t_3x; input n_t_4x; input n_t_5x; input n_t_6x; inout n_t_7x; input n_t_8x; input n_t_9x; assign n_t_22x = ~(n_t_6x & n_t_9x & n_t_5x | n_t_6x & ~n_t_9x & n_t_4x) ^ ~(n_t_6x | n_t_9x & n_t_2x | ~n_t_9x & n_t_3x) ^ ~(~n_t_1x & n_t_14x); assign n_t_7x = ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) ^ ~(n_t_8x | n_t_10x & n_t_2x | ~n_t_10x & n_t_3x) ^ ~(~n_t_1x & ~(n_t_6x | n_t_9x & n_t_2x | ~n_t_9x & n_t_3x) | ~n_t_1x & n_t_14x & ~(n_t_6x & n_t_9x & n_t_5x | n_t_6x & ~n_t_9x & n_t_4x)); assign n_t_21x = ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) ^ ~(n_t_12x | n_t_11x & n_t_2x | ~n_t_11x & n_t_3x) ^ ~(~n_t_1x & ~(n_t_8x | n_t_10x & n_t_2x | ~n_t_10x & n_t_3x) | ~n_t_1x & ~(n_t_6x | n_t_9x & n_t_2x | ~n_t_9x & n_t_3x) & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) | ~n_t_1x & n_t_14x & l0 & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x)); assign n_t_20x = ~(n_t_13x & n_t_15x & n_t_5x | n_t_13x & ~n_t_15x & n_t_4x) ^ ~(n_t_13x | n_t_15x & n_t_2x | ~n_t_15x & n_t_3x) ^ ~(~n_t_1x & ~(n_t_12x | n_t_11x & n_t_2x | ~n_t_11x & n_t_3x) | | ~n_t_1x & ~(n_t_8x | n_t_10x & n_t_2x | ~n_t_10x & n_t_3x) & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) | ~n_t_1x & ~(n_t_6x | n_t_9x & n_t_2x | ~n_t_9x & n_t_3x) & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) | ~n_t_1x & n_t_14x & l0 & l1 & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x)); assign n_t_19x = n_t_22x & n_t_7x & n_t_21x & n_t_20x; assign n_t_18x = ~(~(n_t_6x & n_t_9x & n_t_5x | n_t_6x & ~n_t_9x & n_t_4x) & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) & ~(n_t_13x & n_t_15x & n_t_5x | n_t_13x & ~n_t_15x & n_t_4x)); assign n_t_16x = ~(~(n_t_6x | n_t_9x & n_t_2x | ~n_t_9x & n_t_3x) & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) & ~(n_t_13x & n_t_15x & n_t_5x | n_t_13x & ~n_t_15x & n_t_4x) | i); assign n_t_17x = ~(n_t_6x & n_t_9x & n_t_5x | n_t_6x & ~n_t_9x & n_t_4x) & ~(n_t_8x & n_t_10x & n_t_5x | n_t_8x & ~n_t_10x & n_t_4x) & ~(n_t_12x & n_t_11x & n_t_5x | n_t_12x & ~n_t_11x & n_t_4x) & ~(n_t_13x & n_t_15x & n_t_5x | n_t_13x & ~n_t_15x & n_t_4x) & n_t_14x | ~n_t_16x; // open collector 'wire-or's endmodule