// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn7453 
// n_t_1x = !(n_t_3x & n_t_2x
//       # n_t_4x & n_t_5x
//       # n_t_6x & n_t_7x); 
// n_t_8x = !n_t_1x; 
module m160x (n3v, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_20x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_29x, n_t_2x, n_t_30x, n_t_31x, n_t_32x, n_t_33x, n_t_34x, n_t_35x, n_t_36x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_9x);
input n3v;
input n_t_10x;
input n_t_11x;
input n_t_12x;
input n_t_13x;
input n_t_14x;
input n_t_15x;
output n_t_16x;
output n_t_17x;
output n_t_18x;
output n_t_19x;
output n_t_20x;
input n_t_23x;
input n_t_24x;
input n_t_25x;
input n_t_26x;
input n_t_27x;
input n_t_28x;
input n_t_29x;
input n_t_2x;
input n_t_30x;
output n_t_31x;
output n_t_32x;
output n_t_33x;
output n_t_34x;
output n_t_35x;
output n_t_36x;
input n_t_3x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_9x;


wire n_t_1x;
wire n_t_21x;
wire n_t_22x;
wire n_t_8x;
assign n_t_16x = n_t_1x;
// e2: sn7460 
// n_t_1x = !(n_t_9x & n_t_10x & n_t_11x & n_t_12x); 
// n_t_8x = !n_t_1x; 
// n_t_1x = !(n_t_15x & n_t_14x & n_t_13x & n3v); 
// n_t_8x = !n_t_1x; 
// e3: sn7450 
// e4: sn7460 
// n_t_22x = !(n_t_25x & n_t_24x & n_t_23x & n_t_26x); 
// n_t_21x = !n_t_22x; 
// n_t_22x = !(n_t_27x & n_t_30x & n_t_28x & n_t_29x); 
// n_t_21x = !n_t_22x; 
// open collector 'wire-or's 
assign n_t_1x = ~((n_t_3x & n_t_2x
                    | n_t_4x & n_t_5x
                    | n_t_6x & n_t_7x)
                   | (n_t_9x & n_t_10x & n_t_11x & n_t_12x)
                   | (n_t_15x & n_t_14x & n_t_13x & n3v));
assign n_t_21x = ~n_t_22x;
assign n_t_22x = ~((n_t_25x & n_t_24x & n_t_23x & n_t_26x)
                    | (n_t_27x & n_t_30x & n_t_28x & n_t_29x));
assign n_t_8x = ~n_t_1x;
endmodule