~/Verilog/bin/topld.pl M162A
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: cpol_use ne cpol_use15_5axial
info: 7430n ne dil14
info: 7430n ne dil14
info: edge_2connector ne edge_con2
warning: making u$2/edge_2connector/ a connector
~/Verilog/bin/smaller.pl M162A.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M162AX.PLD || (rm M162AX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M162AX.PLD >vv || (rm vv; exit 1)
mv vv M162A.v
rm M162AX.PLD