// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: cpol_use 
// c13: cpol_use 
// c14: cpol_use 
// e1: sn7420 
module m162b (n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_2x, n_t_34x, n_t_35x, n_t_36x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x);
inout n_t_17x;
input n_t_18x;
input n_t_19x;
input n_t_1x;
input n_t_20x;
input n_t_21x;
input n_t_22x;
input n_t_23x;
input n_t_24x;
input n_t_25x;
input n_t_2x;
inout n_t_34x;
output n_t_35x;
output n_t_36x;
input n_t_3x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;


wire n_t_10x;
wire n_t_11x;
wire n_t_12x;
wire n_t_13x;
wire n_t_14x;
wire n_t_15x;
wire n_t_16x;
wire n_t_26x;
wire n_t_27x;
wire n_t_28x;
wire n_t_29x;
wire n_t_30x;
wire n_t_31x;
wire n_t_32x;
wire n_t_33x;
wire n_t_9x;
assign n_t_15x = ~(n_t_3x & n_t_1x & n_t_5x & n_t_6x);
assign n_t_9x = ~(n_t_8x & n_t_6x & n_t_5x & n_t_2x);
// e2: sn7420 
assign n_t_14x = ~(n_t_7x & n_t_5x & n_t_1x & n_t_2x);
assign n_t_11x = ~(n_t_3x & n_t_5x & n_t_7x & n_t_8x);
// e3: sn7430 
assign n_t_17x = ~(n_t_11x & n_t_14x & n_t_13x & n_t_10x & n_t_12x & n_t_16x & n_t_15x & n_t_9x);
// e4: sn7420 
assign n_t_10x = ~(n_t_3x & n_t_4x & n_t_6x & n_t_8x);
assign n_t_16x = ~(n_t_6x & n_t_4x & n_t_1x & n_t_2x);
// e5: sn7420 
assign n_t_12x = ~(n_t_8x & n_t_7x & n_t_4x & n_t_2x);
assign n_t_13x = ~(n_t_3x & n_t_1x & n_t_4x & n_t_7x);
// e6: sn7420 
assign n_t_35x = ~n_t_34x;
assign n_t_36x = ~n_t_17x;
// e7: sn7420 
assign n_t_32x = ~(n_t_20x & n_t_18x & n_t_22x & n_t_23x);
assign n_t_26x = ~(n_t_25x & n_t_23x & n_t_22x & n_t_19x);
// e8: sn7420 
assign n_t_31x = ~(n_t_24x & n_t_22x & n_t_18x & n_t_19x);
assign n_t_28x = ~(n_t_20x & n_t_22x & n_t_24x & n_t_25x);
// e9: sn7430 
assign n_t_34x = ~(n_t_27x & n_t_29x & n_t_33x & n_t_30x & n_t_32x & n_t_31x & n_t_26x & n_t_28x);
// e10: sn7420 
assign n_t_27x = ~(n_t_20x & n_t_21x & n_t_23x & n_t_25x);
assign n_t_33x = ~(n_t_23x & n_t_21x & n_t_18x & n_t_19x);
// e11: sn7420 
assign n_t_29x = ~(n_t_25x & n_t_24x & n_t_21x & n_t_19x);
assign n_t_30x = ~(n_t_20x & n_t_18x & n_t_21x & n_t_24x);
// open collector 'wire-or's 
endmodule