~/Verilog/bin/topld.pl M162X
info: 7430n ne dil14
info: 7430n ne dil14
info: edge_2connector ne edge_con2
warning: making u$2/edge_2connector/ a connector
~/Verilog/bin/smaller.pl M162X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M162XX.PLD || (rm M162XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M162XX.PLD >vv || (rm vv; exit 1)
mv vv M162X.v
rm M162XX.PLD