// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// e1: sn7400 
module m165x (n3v3, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
input n3v3;
input n_t_10x;
output n_t_11x;
output n_t_12x;
input n_t_13x;
output n_t_14x;
output n_t_15x;
input n_t_16x;
output n_t_17x;
output n_t_18x;
input n_t_19x;
input n_t_1x;
output n_t_20x;
output n_t_21x;
input n_t_22x;
output n_t_23x;
output n_t_24x;
input n_t_2x;
output n_t_3x;
output n_t_4x;
output n_t_5x;
output n_t_6x;
input n_t_7x;
output n_t_8x;
output n_t_9x;


assign n_t_4x = ~(n_t_1x & n3v3);
assign n_t_6x = ~(n3v3 & n_t_2x);
assign n_t_9x = ~(n_t_7x & n3v3);
assign n_t_12x = ~(n_t_10x & n3v3);
// e2: dec3001n 
assign n_t_3x = (n_t_1x & n3v3);
assign n_t_5x = (n3v3 & n_t_2x);
assign n_t_8x = (n_t_7x & n3v3);
assign n_t_11x = (n_t_10x & n3v3);
// e3: sn7400 
assign n_t_15x = ~(n_t_13x & n3v3);
assign n_t_18x = ~(n3v3 & n_t_16x);
assign n_t_21x = ~(n_t_19x & n3v3);
assign n_t_24x = ~(n_t_22x & n3v3);
// e4: dec3001n 
assign n_t_14x = (n_t_13x & n3v3);
assign n_t_17x = (n3v3 & n_t_16x);
assign n_t_20x = (n_t_19x & n3v3);
assign n_t_23x = (n_t_22x & n3v3);
// open collector 'wire-or's 
endmodule