~/Verilog/bin/topld.pl M168X
info: 7485n ne dil16
info: 7485n ne dil16
info: 7485n ne dil16
info: single ne edge_con2
warning: making u$1/single/ a connector
~/Verilog/bin/smaller.pl M168X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M168XX.PLD || (rm M168XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M168XX.PLD >vv || (rm vv; exit 1)
mv vv M168X.v
rm M168XX.PLD