~/Verilog/bin/topld.pl M169X
info: 7453n ne dil14
info: 7453n ne dil14
info: 7400n ne dil14
info: 7453n ne dil14
info: 7453n ne dil14
info: edge_2connector ne edge_con2
warning: making u$2/edge_2connector/ a connector
~/Verilog/bin/smaller.pl M169X.PLD >vv || (rm vv; exit 1)
8 signals were removed:
  gdollar_1: !gdollar_0
  gdollar_3: !gdollar_2
  gdollar_5: !gdollar_4
  gdollar_7: !gdollar_6
  n_t_1x: gdollar_0
  n_t_22x: gdollar_6
  n_t_23x: gdollar_4
  n_t_7x: gdollar_2
~/Verilog/bin/smaller.pl vv >M169XX.PLD || (rm M169XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M169XX.PLD >vv || (rm vv; exit 1)
mv vv M169X.v
rm M169XX.PLD