// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn74153 
module m1701d (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_2x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
output n_t_10x;
input n_t_11x;
input n_t_12x;
output n_t_13x;
output n_t_14x;
input n_t_15x;
input n_t_16x;
input n_t_17x;
input n_t_18x;
input n_t_19x;
input n_t_1x;
input n_t_20x;
output n_t_21x;
input n_t_22x;
input n_t_23x;
input n_t_24x;
input n_t_25x;
input n_t_26x;
output n_t_27x;
output n_t_28x;
input n_t_2x;
input n_t_3x;
input n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;
input n_t_9x;


assign n_t_14x = ~n_t_9x & (~pad{1} & ~n_t_11x & n_t_1x
                             | ~pad{1} & n_t_11x & n_t_2x
                             | pad{1} & ~n_t_11x & n_t_3x
                             | pad{1} & n_t_11x & n_t_4x);
assign n_t_13x = ~n_t_12x & (~pad{1} & ~n_t_11x & n_t_5x
                              | ~pad{1} & n_t_11x & n_t_6x
                              | pad{1} & ~n_t_11x & n_t_7x
                              | pad{1} & n_t_11x & n_t_8x);
// e2: sn74153 
assign n_t_27x = ~n_t_19x & (~pad{1} & ~n_t_26x & n_t_15x
                              | ~pad{1} & n_t_26x & n_t_16x
                              | pad{1} & ~n_t_26x & n_t_17x
                              | pad{1} & n_t_26x & n_t_18x);
assign n_t_28x = ~n_t_20x & (~pad{1} & ~n_t_26x & n_t_22x
                              | ~pad{1} & n_t_26x & n_t_23x
                              | pad{1} & ~n_t_26x & n_t_24x
                              | pad{1} & n_t_26x & n_t_25x);
// open collector 'wire-or's 
endmodule