~/Verilog/bin/topld.pl M1701X
info: cpol_use ne cpol_use20_8axial
info: single ne edge_con2
warning: making u$2/single/ a connector
~/Verilog/bin/smaller.pl M1701X.PLD >vv || (rm vv; exit 1)
0 signals were removed:
~/Verilog/bin/smaller.pl vv >M1701XX.PLD || (rm M1701XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M1701XX.PLD >vv || (rm vv; exit 1)
mv vv M1701X.v
rm M1701XX.PLD