// this file is generated by topld.pl // please don't edit it. // input pins // output pins // internal nodes // code nodes // equations // c1: c_us // c2: c_us // c3: c_us // c4: c_us // c5: c_us // c6: c_us // c7: c_us // c8: c_us // c9: c_us // c10: c_us // c11: c_us // c12: c_us // c13: c_us // c14: c_us // c15: c_us // c16: c_us // c17: c_us // c18: c_us // c19: c_us // c20: c_us // c21: c_us // c22: c_us // c23: c_us // c24: c_us // c25: c_us // c26: c_us // c27: c_us // c28: c_us // c29: c_us // c30: c_us // c31: c_us // c32: c_us // c33: c_us // c34: c_us // c100: cpol_use // c101: cpol_use // c102: cpol_use // e1: sn7430 module m1705b (n3v1, n3v2, n3v3, n3v4, n_t_103x, n_t_165x, n_t_171x, n_t_172x, n_t_24x, n_t_273x, n_t_29x, n_t_31x, n_t_32x, n_t_33x, n_t_36x, n_t_38x, n_t_39x, n_t_40x, n_t_41x, n_t_42x, n_t_45x, n_t_476x, n_t_488x, n_t_491x, n_t_586x, n_t_69x, ad00h, ad01h, ad02h, ad03h, ad04h, ad05h, ad06h, ad07h, ad08h, ad09h, ad10h, ad11h, adoneh, adonel, aflagh, ainith, aiot4l, areadyh, areadyl, astrobeh, astrobel, bd00h, bd01h, bd02h, bd03h, bd04h, bd05h, bd06h, bd07h, bd08h, bd09h, bd10h, bd11h, bdoneh, bdonel, bflagh, binith, biot4l, breadyh, breadyl, bstrobeh, bstrobel, c0_l, c1_l, data0_l, data10_l, data11_l, data1_l, data2_l, data3_l, data4_l, data5_l, data6_l, data7_l, data8_l, data9_l, initialize, initializeh, int_rqst_l, internal_io_l, io_pause_l, md03_l, md03h, md03l, md04_l, md04h, md04l, md05_l, md05h, md05l, md06_l, md06h, md06l, md07_l, md07h, md07l, md08_l, md08h, md08l, md09_l, md10_l, md11_l, n_t_280x, n_t_483x, n_t_526x, n_t_528x, n_t_530x, n_t_57x, n_t_60x, n_t_76x, skip_l, tp3); output n3v1; input n3v2; input n3v3; input n3v4; input n_t_103x; input n_t_165x; input n_t_171x; input n_t_172x; input n_t_24x; output n_t_273x; input n_t_29x; input n_t_31x; input n_t_32x; input n_t_33x; input n_t_36x; input n_t_38x; input n_t_39x; input n_t_40x; input n_t_41x; input n_t_42x; input n_t_45x; output n_t_476x; output n_t_488x; output n_t_491x; output n_t_586x; output n_t_69x; output ad00h; output ad01h; output ad02h; output ad03h; output ad04h; output ad05h; output ad06h; output ad07h; output ad08h; output ad09h; output ad10h; output ad11h; output adoneh; inout adonel; output aflagh; output ainith; output aiot4l; output areadyh; output areadyl; output astrobeh; output astrobel; output bd00h; output bd01h; output bd02h; output bd03h; output bd04h; output bd05h; output bd06h; output bd07h; output bd08h; output bd09h; output bd10h; output bd11h; output bdoneh; inout bdonel; output bflagh; output binith; output biot4l; output breadyh; output breadyl; output bstrobeh; output bstrobel; output c0_l; inout c1_l; inout data0_l; inout data10_l; inout data11_l; inout data1_l; inout data2_l; inout data3_l; inout data4_l; inout data5_l; inout data6_l; inout data7_l; inout data8_l; inout data9_l; input initialize; inout initializeh; inout int_rqst_l; inout internal_io_l; input io_pause_l; input md03_l; inout md03h; output md03l; input md04_l; inout md04h; output md04l; input md05_l; inout md05h; output md05l; input md06_l; inout md06h; output md06l; input md07_l; inout md07h; output md07l; input md08_l; inout md08h; output md08l; input md09_l; input md10_l; input md11_l; input n_t_280x; input n_t_483x; input n_t_526x; input n_t_528x; input n_t_530x; input n_t_57x; input n_t_60x; input n_t_76x; inout skip_l; input tp3; reg actlflgh_m; reg ad00_m; reg ad01_m; reg ad02_m; reg ad03_m; reg ad04_m; reg ad05_m; reg ad06_m; reg ad07_m; reg ad08_m; reg ad09_m; reg ad10_m; reg ad11_m; reg adflag_m; reg aintenh_m; reg bctlflgh_m; reg bd00_m; reg bd01_m; reg bd02_m; reg bd03_m; reg bd04_m; reg bd05_m; reg bd06_m; reg bd07_m; reg bd08_m; reg bd09_m; reg bd10_m; reg bd11_m; reg bdflag_m; reg bintenh_m; reg bd02; reg bd03; reg bd01; reg bd00; reg ad00; reg ad01; reg ad03; reg ad02; reg bdflag; reg adflag; reg bd06; reg bd07; reg bd05; reg bd04; reg ad04; reg ad05; reg ad07; reg ad06; reg bintenh; reg aintenh; reg bctlflgh; reg actlflgh; reg bd10; reg bd11; reg bd09; reg bd08; reg ad08; reg ad09; reg ad11; reg ad10; wire aiot0l; wire aiot1l; wire aiot2l; wire aiot3l; wire aiot5l; wire aiot6l; wire aiot7l; wire aiotl; wire aready; wire biot0l; wire biot1l; wire biot2l; wire biot3l; wire biot5l; wire biot6l; wire biot7l; wire biotl; wire bready; wire n_t_118x; wire n_t_119x; wire n_t_120x; wire n_t_136x; wire n_t_146x; wire n_t_193x; wire n_t_194x; wire n_t_199x; wire n_t_20x; wire n_t_217x; wire n_t_219x; wire n_t_332x; wire n_t_362x; wire n_t_79x; assign biotl = ~(n_t_29x & n_t_38x & n_t_24x & n_t_36x & ~io_pause_l & ~io_pause_l & n_t_33x & n_t_32x); // e2: sn7430 assign aiotl = ~(n_t_39x & n_t_40x & n_t_41x & n_t_42x & ~io_pause_l & ~io_pause_l & n_t_31x & n_t_45x); // e3: sn7404 // e5: ds8838 // data3_l = !(bd03 & biot5l & biot5l); // data2_l = !(bd02 & biot5l & biot5l); // data0_l = !(bd00 & biot5l & biot5l); // data1_l = !(bd01 & biot5l & biot5l); // e6: sn74175 always @(n_t_79x, initializeh, data2_l) if (initializeh) begin bd02_m <= 1'b0; end else if (~(n_t_79x)) begin bd02_m <= ~data2_l; end always @(n_t_79x, initializeh, bd02_m) if (initializeh) begin bd02 <= 1'b0; end else if (n_t_79x) begin bd02 <= bd02_m; end always @(n_t_79x, initializeh, data3_l) if (initializeh) begin bd03_m <= 1'b0; end else if (~(n_t_79x)) begin bd03_m <= ~data3_l; end always @(n_t_79x, initializeh, bd03_m) if (initializeh) begin bd03 <= 1'b0; end else if (n_t_79x) begin bd03 <= bd03_m; end always @(n_t_79x, initializeh, data1_l) if (initializeh) begin bd01_m <= 1'b0; end else if (~(n_t_79x)) begin bd01_m <= ~data1_l; end always @(n_t_79x, initializeh, bd01_m) if (initializeh) begin bd01 <= 1'b0; end else if (n_t_79x) begin bd01 <= bd01_m; end always @(n_t_79x, initializeh, data0_l) if (initializeh) begin bd00_m <= 1'b0; end else if (~(n_t_79x)) begin bd00_m <= ~data0_l; end always @(n_t_79x, initializeh, bd00_m) if (initializeh) begin bd00 <= 1'b0; end else if (n_t_79x) begin bd00 <= bd00_m; end // e7: sn7437 assign bd03h = bd03; assign bd02h = bd02; assign bd01h = bd01; assign bd00h = bd00; // e8: sn7400 assign n_t_118x = ~(aintenh & adflag); assign n_t_120x = ~(~aiot2l & adflag); assign n_t_119x = ~(bdflag & ~biot2l); // e9: n8881n // data3_l = !(ad03 & !aiot5l); // data2_l = !(!aiot5l & ad02); // data0_l = !(ad00 & !aiot5l); // data1_l = !(!aiot5l & ad01); // e10: sn74175 always @(n_t_20x, initializeh, data0_l) if (initializeh) begin ad00_m <= 1'b0; end else if (~(n_t_20x)) begin ad00_m <= ~data0_l; end always @(n_t_20x, initializeh, ad00_m) if (initializeh) begin ad00 <= 1'b0; end else if (n_t_20x) begin ad00 <= ad00_m; end always @(n_t_20x, initializeh, data1_l) if (initializeh) begin ad01_m <= 1'b0; end else if (~(n_t_20x)) begin ad01_m <= ~data1_l; end always @(n_t_20x, initializeh, ad01_m) if (initializeh) begin ad01 <= 1'b0; end else if (n_t_20x) begin ad01 <= ad01_m; end always @(n_t_20x, initializeh, data3_l) if (initializeh) begin ad03_m <= 1'b0; end else if (~(n_t_20x)) begin ad03_m <= ~data3_l; end always @(n_t_20x, initializeh, ad03_m) if (initializeh) begin ad03 <= 1'b0; end else if (n_t_20x) begin ad03 <= ad03_m; end always @(n_t_20x, initializeh, data2_l) if (initializeh) begin ad02_m <= 1'b0; end else if (~(n_t_20x)) begin ad02_m <= ~data2_l; end always @(n_t_20x, initializeh, ad02_m) if (initializeh) begin ad02 <= 1'b0; end else if (n_t_20x) begin ad02 <= ad02_m; end // e11: sn7437 assign ad02h = ad02; assign ad03h = ad03; assign ad01h = ad01; assign ad00h = ad00; // e12: sn7474 always @(bready, n_t_136x, n3v4, n3v4) if (~n_t_136x) begin bdflag_m <= 1'b0; end else if (~n3v4) begin bdflag_m <= 1'b1; end else if (~(bready)) begin bdflag_m <= n3v4; end always @(bready, n_t_136x, n3v4, bdflag_m) if (~n_t_136x) begin bdflag <= 1'b0; end else if (~n3v4) begin bdflag <= 1'b1; end else if (bready) begin bdflag <= bdflag_m; end always @(aready, n_t_146x, n3v4, n3v4) if (~n_t_146x) begin adflag_m <= 1'b0; end else if (~n3v4) begin adflag_m <= 1'b1; end else if (~(aready)) begin adflag_m <= n3v4; end always @(aready, n_t_146x, n3v4, adflag_m) if (~n_t_146x) begin adflag <= 1'b0; end else if (~n3v4) begin adflag <= 1'b1; end else if (aready) begin adflag <= adflag_m; end // e13: sn7408 assign n_t_193x = (biot7l & ~initializeh); assign n_t_194x = (~initializeh & aiot7l); assign bready = (n_t_219x & ~n_t_57x); assign aready = (n_t_217x & ~n_t_60x); // e14: ds8837n assign md05h = ~md05_l; assign md04h = ~md04_l; assign md03h = ~md03_l; assign md06h = ~md06_l; assign md07h = ~md07_l; // e15: sn7404 assign md04l = ~md04h; assign md05l = ~md05h; assign md08l = ~md08h; assign md07l = ~md07h; assign md06l = ~md06h; assign md03l = ~md03h; // e16: sn7400 assign n_t_199x = ~(bdflag & bintenh); assign n_t_20x = ~(~aiot3l & ~tp3); assign n_t_79x = ~(~tp3 & ~biot3l); // e19: ds8838 // data7_l = !(bd07 & biot5l & biot5l); // data6_l = !(bd06 & biot5l & biot5l); // data4_l = !(bd04 & biot5l & biot5l); // data5_l = !(bd05 & biot5l & biot5l); // e20: sn74175 always @(n_t_79x, initializeh, data6_l) if (initializeh) begin bd06_m <= 1'b0; end else if (~(n_t_79x)) begin bd06_m <= ~data6_l; end always @(n_t_79x, initializeh, bd06_m) if (initializeh) begin bd06 <= 1'b0; end else if (n_t_79x) begin bd06 <= bd06_m; end always @(n_t_79x, initializeh, data7_l) if (initializeh) begin bd07_m <= 1'b0; end else if (~(n_t_79x)) begin bd07_m <= ~data7_l; end always @(n_t_79x, initializeh, bd07_m) if (initializeh) begin bd07 <= 1'b0; end else if (n_t_79x) begin bd07 <= bd07_m; end always @(n_t_79x, initializeh, data5_l) if (initializeh) begin bd05_m <= 1'b0; end else if (~(n_t_79x)) begin bd05_m <= ~data5_l; end always @(n_t_79x, initializeh, bd05_m) if (initializeh) begin bd05 <= 1'b0; end else if (n_t_79x) begin bd05 <= bd05_m; end always @(n_t_79x, initializeh, data4_l) if (initializeh) begin bd04_m <= 1'b0; end else if (~(n_t_79x)) begin bd04_m <= ~data4_l; end always @(n_t_79x, initializeh, bd04_m) if (initializeh) begin bd04 <= 1'b0; end else if (n_t_79x) begin bd04 <= bd04_m; end // e21: sn7437 assign bd07h = bd07; assign bd06h = bd06; assign bd04h = bd04; assign bd05h = bd05; // e23: sn7437 assign adoneh = ~(adonel & n3v3); assign bdonel = ~(~bdflag & n_t_136x); assign bdoneh = ~(bdonel & n3v3); assign adonel = ~(~adflag & n_t_146x); // e24: n8881n // data7_l = !(ad07 & !aiot5l); // data6_l = !(!aiot5l & ad06); // data4_l = !(ad04 & !aiot5l); // data5_l = !(!aiot5l & ad05); // e25: sn74175 always @(n_t_20x, initializeh, data4_l) if (initializeh) begin ad04_m <= 1'b0; end else if (~(n_t_20x)) begin ad04_m <= ~data4_l; end always @(n_t_20x, initializeh, ad04_m) if (initializeh) begin ad04 <= 1'b0; end else if (n_t_20x) begin ad04 <= ad04_m; end always @(n_t_20x, initializeh, data5_l) if (initializeh) begin ad05_m <= 1'b0; end else if (~(n_t_20x)) begin ad05_m <= ~data5_l; end always @(n_t_20x, initializeh, ad05_m) if (initializeh) begin ad05 <= 1'b0; end else if (n_t_20x) begin ad05 <= ad05_m; end always @(n_t_20x, initializeh, data7_l) if (initializeh) begin ad07_m <= 1'b0; end else if (~(n_t_20x)) begin ad07_m <= ~data7_l; end always @(n_t_20x, initializeh, ad07_m) if (initializeh) begin ad07 <= 1'b0; end else if (n_t_20x) begin ad07 <= ad07_m; end always @(n_t_20x, initializeh, data6_l) if (initializeh) begin ad06_m <= 1'b0; end else if (~(n_t_20x)) begin ad06_m <= ~data6_l; end always @(n_t_20x, initializeh, ad06_m) if (initializeh) begin ad06 <= 1'b0; end else if (n_t_20x) begin ad06 <= ad06_m; end // e26: sn7437 assign ad05h = ad05; assign ad04h = ad04; assign ad06h = ad06; assign ad07h = ad07; // e27: sn7437 assign binith = initializeh; assign ainith = initializeh; // e28: n8881n // c1_l = c1_l; // c0_l = c1_l; // skip_l = skip_l; // internal_io_l = internal_io_l; // e29: sn7442 assign biot0l = ~(~biotl & md09_l & md10_l & md11_l); assign biot1l = ~(~biotl & md09_l & md10_l & ~md11_l); assign biot2l = ~(~biotl & md09_l & ~md10_l & md11_l); assign biot3l = ~(~biotl & md09_l & ~md10_l & ~md11_l); assign biot4l = ~(~biotl & ~md09_l & md10_l & md11_l); assign biot5l = ~(~biotl & ~md09_l & md10_l & ~md11_l); assign biot6l = ~(~biotl & ~md09_l & ~md10_l & md11_l); assign biot7l = ~(~biotl & ~md09_l & ~md10_l & ~md11_l); // e30: sn7474 always @(n3v2, n_t_362x, biot1l, 1'b1) if (~n_t_362x) begin bintenh_m <= 1'b0; end else if (~biot1l) begin bintenh_m <= 1'b1; end else if (~(n3v2)) begin bintenh_m <= 1'b1; end always @(n3v2, n_t_362x, biot1l, bintenh_m) if (~n_t_362x) begin bintenh <= 1'b0; end else if (~biot1l) begin bintenh <= 1'b1; end else if (n3v2) begin bintenh <= bintenh_m; end always @(n3v2, n_t_332x, aiot1l, 1'b1) if (~n_t_332x) begin aintenh_m <= 1'b0; end else if (~aiot1l) begin aintenh_m <= 1'b1; end else if (~(n3v2)) begin aintenh_m <= 1'b1; end always @(n3v2, n_t_332x, aiot1l, aintenh_m) if (~n_t_332x) begin aintenh <= 1'b0; end else if (~aiot1l) begin aintenh <= 1'b1; end else if (n3v2) begin aintenh <= aintenh_m; end // e31: sn7486 assign bflagh = ~(n_t_171x ^ bctlflgh); assign aflagh = ~(n_t_172x ^ actlflgh); assign n_t_219x = n_t_280x ^ n_t_165x; assign n_t_217x = n_t_76x ^ n_t_103x; // e32: ds8837n assign md08h = ~md08_l; // e33: sn7442 assign aiot0l = ~(~aiotl & md09_l & md10_l & md11_l); assign aiot1l = ~(~aiotl & md09_l & md10_l & ~md11_l); assign aiot2l = ~(~aiotl & md09_l & ~md10_l & md11_l); assign aiot3l = ~(~aiotl & md09_l & ~md10_l & ~md11_l); assign aiot4l = ~(~aiotl & ~md09_l & md10_l & md11_l); assign aiot5l = ~(~aiotl & ~md09_l & md10_l & ~md11_l); assign aiot6l = ~(~aiotl & ~md09_l & ~md10_l & md11_l); assign aiot7l = ~(~aiotl & ~md09_l & ~md10_l & ~md11_l); // e34: sn7408 assign n_t_146x = (aiot3l & ~initialize); assign n_t_332x = (~initialize & aiot0l); assign n_t_136x = (biot3l & ~initialize); assign n_t_362x = (biot0l & ~initialize); // e35: sn7474 always @(n3v2, n_t_193x, biot6l, 1'b1) if (~n_t_193x) begin bctlflgh_m <= 1'b0; end else if (~biot6l) begin bctlflgh_m <= 1'b1; end else if (~(n3v2)) begin bctlflgh_m <= 1'b1; end always @(n3v2, n_t_193x, biot6l, bctlflgh_m) if (~n_t_193x) begin bctlflgh <= 1'b0; end else if (~biot6l) begin bctlflgh <= 1'b1; end else if (n3v2) begin bctlflgh <= bctlflgh_m; end always @(n3v2, n_t_194x, aiot6l, 1'b1) if (~n_t_194x) begin actlflgh_m <= 1'b0; end else if (~aiot6l) begin actlflgh_m <= 1'b1; end else if (~(n3v2)) begin actlflgh_m <= 1'b1; end always @(n3v2, n_t_194x, aiot6l, actlflgh_m) if (~n_t_194x) begin actlflgh <= 1'b0; end else if (~aiot6l) begin actlflgh <= 1'b1; end else if (n3v2) begin actlflgh <= actlflgh_m; end // e36: ds8838 // data11_l = !(bd11 & biot5l & biot5l); // data10_l = !(bd10 & biot5l & biot5l); // data8_l = !(bd08 & biot5l & biot5l); // data9_l = !(bd09 & biot5l & biot5l); // e37: sn74175 always @(n_t_79x, initializeh, data10_l) if (initializeh) begin bd10_m <= 1'b0; end else if (~(n_t_79x)) begin bd10_m <= ~data10_l; end always @(n_t_79x, initializeh, bd10_m) if (initializeh) begin bd10 <= 1'b0; end else if (n_t_79x) begin bd10 <= bd10_m; end always @(n_t_79x, initializeh, data11_l) if (initializeh) begin bd11_m <= 1'b0; end else if (~(n_t_79x)) begin bd11_m <= ~data11_l; end always @(n_t_79x, initializeh, bd11_m) if (initializeh) begin bd11 <= 1'b0; end else if (n_t_79x) begin bd11 <= bd11_m; end always @(n_t_79x, initializeh, data9_l) if (initializeh) begin bd09_m <= 1'b0; end else if (~(n_t_79x)) begin bd09_m <= ~data9_l; end always @(n_t_79x, initializeh, bd09_m) if (initializeh) begin bd09 <= 1'b0; end else if (n_t_79x) begin bd09 <= bd09_m; end always @(n_t_79x, initializeh, data8_l) if (initializeh) begin bd08_m <= 1'b0; end else if (~(n_t_79x)) begin bd08_m <= ~data8_l; end always @(n_t_79x, initializeh, bd08_m) if (initializeh) begin bd08 <= 1'b0; end else if (n_t_79x) begin bd08 <= bd08_m; end // e38: sn7437 assign bd11h = bd11; assign bd10h = bd10; assign bd08h = bd08; assign bd09h = bd09; // e39: n8881n // data11_l = !(ad11 & !aiot5l); // data10_l = !(!aiot5l & ad10); // data8_l = !(ad08 & !aiot5l); // data9_l = !(!aiot5l & ad09); // e40: sn74175 always @(n_t_20x, initializeh, data8_l) if (initializeh) begin ad08_m <= 1'b0; end else if (~(n_t_20x)) begin ad08_m <= ~data8_l; end always @(n_t_20x, initializeh, ad08_m) if (initializeh) begin ad08 <= 1'b0; end else if (n_t_20x) begin ad08 <= ad08_m; end always @(n_t_20x, initializeh, data9_l) if (initializeh) begin ad09_m <= 1'b0; end else if (~(n_t_20x)) begin ad09_m <= ~data9_l; end always @(n_t_20x, initializeh, ad09_m) if (initializeh) begin ad09 <= 1'b0; end else if (n_t_20x) begin ad09 <= ad09_m; end always @(n_t_20x, initializeh, data11_l) if (initializeh) begin ad11_m <= 1'b0; end else if (~(n_t_20x)) begin ad11_m <= ~data11_l; end always @(n_t_20x, initializeh, ad11_m) if (initializeh) begin ad11 <= 1'b0; end else if (n_t_20x) begin ad11 <= ad11_m; end always @(n_t_20x, initializeh, data10_l) if (initializeh) begin ad10_m <= 1'b0; end else if (~(n_t_20x)) begin ad10_m <= ~data10_l; end always @(n_t_20x, initializeh, ad10_m) if (initializeh) begin ad10 <= 1'b0; end else if (n_t_20x) begin ad10 <= ad10_m; end // e41: sn7437 assign ad09h = ad09; assign ad08h = ad08; assign ad10h = ad10; assign ad11h = ad11; // e42: sn7437 assign bstrobeh = ~n_t_483x; assign astrobel = ~n_t_530x; assign bstrobel = ~n_t_528x; assign astrobeh = ~n_t_526x; // e43: sn7437 // e45: n8881n // int_rqst_l = int_rqst_l; // initializeh = initialize; // open collector 'wire-or's assign c0_l = ~c1_l? 1'b0: 1'bz; assign c1_l = ~(~(~(aiot5l & biot5l)))? ~(~(aiot5l & biot5l)): 1'bz; assign data0_l = (bd00 & biot5l & biot5l) | (ad00 & ~aiot5l)? 1'b0: 1'bz; assign data10_l = (bd10 & biot5l & biot5l) | (~aiot5l & ad10)? 1'b0: 1'bz; assign data11_l = (bd11 & biot5l & biot5l) | (ad11 & ~aiot5l)? 1'b0: 1'bz; assign data1_l = (bd01 & biot5l & biot5l) | (~aiot5l & ad01)? 1'b0: 1'bz; assign data2_l = (bd02 & biot5l & biot5l) | (~aiot5l & ad02)? 1'b0: 1'bz; assign data3_l = (bd03 & biot5l & biot5l) | (ad03 & ~aiot5l)? 1'b0: 1'bz; assign data4_l = (bd04 & biot5l & biot5l) | (ad04 & ~aiot5l)? 1'b0: 1'bz; assign data5_l = (bd05 & biot5l & biot5l) | (~aiot5l & ad05)? 1'b0: 1'bz; assign data6_l = (bd06 & biot5l & biot5l) | (~aiot5l & ad06)? 1'b0: 1'bz; assign data7_l = (bd07 & biot5l & biot5l) | (ad07 & ~aiot5l)? 1'b0: 1'bz; assign data8_l = (bd08 & biot5l & biot5l) | (ad08 & ~aiot5l)? 1'b0: 1'bz; assign data9_l = (bd09 & biot5l & biot5l) | (~aiot5l & ad09)? 1'b0: 1'bz; assign initializeh = ~initialize? 1'b0: 1'bz; assign int_rqst_l = ~(~(~(n_t_118x & n_t_199x)))? ~(~(n_t_118x & n_t_199x)): 1'bz; assign internal_io_l = ~(~(~(biotl & aiotl)))? ~(~(biotl & aiotl)): 1'bz; assign skip_l = ~(~(~(n_t_120x & n_t_119x)))? ~(~(n_t_120x & n_t_119x)): 1'bz; endmodule