~/Verilog/bin/topld.pl M1705X
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: cpol_use ne cpol_use20_8axial
info: 7430n ne dil14
info: 74175n ne dil16
info: 7437n ne dil14
info: ds8837n ne dil16
info: 7404n ne dil14
info: 7400n ne dil14
info: dec2501 ne dil14
warning: making e17/dec2501/ a connector
info: 7413n ne dil14
warning: making e18/sn7413/ a connector
info: 8t38 ne ds8641n
info: 7430n ne dil14
info: 74175n ne dil16
info: 7437n ne dil14
info: dec2501 ne dil14
warning: making e22/dec2501/ a connector
info: 7437n ne dil14
info: n8881n ne dil14
info: 74175n ne dil16
info: 7437n ne dil14
info: 7437n ne dil14
info: n8881n ne dil14
info: 7404n ne dil14
info: 7486n ne dil14
info: ds8837n ne dil16
info: 8t38 ne ds8641n
info: 74175n ne dil16
info: 7437n ne dil14
info: n8881n ne dil14
info: 7413n ne dil14
warning: making e4/sn7413/ a connector
info: 74175n ne dil16
info: 7437n ne dil14
info: 7437n ne dil14
info: 7437n ne dil14
info: 74123n ne dil16
warning: making e44/sn74123/ a connector
info: n8881n ne dil14
info: dec2501 ne dil14
warning: making e46/dec2501/ a connector
info: dec2501 ne dil14
warning: making e47/dec2501/ a connector
info: dec2501 ne dil14
warning: making e48/dec2501/ a connector
info: 8t38 ne ds8641n
info: 74175n ne dil16
info: 7437n ne dil14
info: 7400n ne dil14
info: n8881n ne dil14
warning: making j1/dec40pinh/ a connector
warning: making j2/dec40pinh/ a connector
info: (option) ne 275p
warning: making r23/(option)/ a connector
info: (option) ne 275p
warning: making r24/(option)/ a connector
info: quad ne edge_con8
warning: making u$2/quad/ a connector
info: j7mm ne 07
warning: making w1/j7mm/ a connector
info: j7mm ne 07
warning: making w10/j7mm/ a connector
info: j7mm ne 07
warning: making w11/j7mm/ a connector
info: j7mm ne 07
warning: making w12/j7mm/ a connector
info: j7mm ne 07
warning: making w13/j7mm/ a connector
info: j7mm ne 07
warning: making w14/j7mm/ a connector
info: j7mm ne 07
warning: making w15/j7mm/ a connector
info: j7mm ne 07
warning: making w16/j7mm/ a connector
info: j7mm ne 07
warning: making w17/j7mm/ a connector
info: j7mm ne 07
warning: making w18/j7mm/ a connector
info: j7mm ne 07
warning: making w19/j7mm/ a connector
info: j7mm ne 07
warning: making w2/j7mm/ a connector
info: j7mm ne 07
warning: making w20/j7mm/ a connector
info: j7mm ne 07
warning: making w21/j7mm/ a connector
info: j7mm ne 07
warning: making w22/j7mm/ a connector
info: j7mm ne 07
warning: making w23/j7mm/ a connector
info: j7mm ne 07
warning: making w24/j7mm/ a connector
info: j20mm ne 20
warning: making w25/j20mm/ a connector
info: j7mm ne 07
warning: making w26/j7mm/ a connector
info: j20mm ne 20
warning: making w27/j20mm/ a connector
info: j7mm ne 07
warning: making w28/j7mm/ a connector
info: j7mm ne 07
warning: making w29/j7mm/ a connector
info: j7mm ne 07
warning: making w3/j7mm/ a connector
info: j7mm ne 07
warning: making w30/j7mm/ a connector
info: j7mm ne 07
warning: making w31/j7mm/ a connector
info: j7mm ne 07
warning: making w32/j7mm/ a connector
info: j7mm ne 07
warning: making w4/j7mm/ a connector
info: j7mm ne 07
warning: making w5/j7mm/ a connector
info: j7mm ne 07
warning: making w6/j7mm/ a connector
info: j7mm ne 07
warning: making w7/j7mm/ a connector
info: j7mm ne 07
warning: making w8/j7mm/ a connector
info: j7mm ne 07
warning: making w9/j7mm/ a connector
warning: non-bypass capacitor deleted: c33
warning: non-bypass capacitor deleted: c34
~/Verilog/bin/smaller.pl M1705X.PLD >vv || (rm vv; exit 1)
58 signals were removed:
  ad00l: !ad00
  ad01l: !ad01
  ad02l: !ad02
  ad03l: !ad03
  ad04l: !ad04
  ad05l: !ad05
  ad06l: !ad06
  ad07l: !ad07
  ad08l: !ad08
  ad09l: !ad09
  ad10l: !ad10
  ad11l: !ad11
  aiot2h: !aiot2l
  aiot3h: !aiot3l
  bd00l: !bd00
  bd01l: !bd01
  bd02l: !bd02
  bd03l: !bd03
  bd04l: !bd04
  bd05l: !bd05
  bd06l: !bd06
  bd07l: !bd07
  bd08l: !bd08
  bd09l: !bd09
  bd10l: !bd10
  bd11l: !bd11
  biot2h: !biot2l
  biot3h: !biot3l
  data0: !data0_l
  data1: !data1_l
  data10: !data10_l
  data11: !data11_l
  data2: !data2_l
  data3: !data3_l
  data4: !data4_l
  data5: !data5_l
  data6: !data6_l
  data7: !data7_l
  data8: !data8_l
  data9: !data9_l
  initializel: !initialize
  initl: !initializeh
  io_pauseh: !io_pause_l
  md09h: !md09_l
  md10h: !md10_l
  md11h: !md11_l
  n_t_147x: !adflag
  n_t_151x: !bdflag
  n_t_196x: !internal_io_l
  n_t_1x: !aiot5l
  n_t_337x: !c1_l
  n_t_347x: !bflagh
  n_t_350x: !int_rqst_l
  n_t_386x: !aflagh
  n_t_53x: !skip_l
  n_t_56x: !n_t_57x
  n_t_64x: !n_t_60x
  tp3l: !tp3
~/Verilog/bin/smaller.pl vv >M1705XX.PLD || (rm M1705XX.PLD; exit 1)
0 signals were removed:
~/Verilog/bin/cupl2v.pl M1705XX.PLD >vv || (rm vv; exit 1)
mv vv M1705X.v
rm M1705XX.PLD