// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn7400 
module m203b (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_29x, n_t_2x, n_t_30x, n_t_31x, n_t_32x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
inout n_t_10x;
input n_t_11x;
input n_t_12x;
inout n_t_13x;
inout n_t_14x;
input n_t_15x;
input n_t_16x;
inout n_t_17x;
inout n_t_18x;
input n_t_19x;
inout n_t_1x;
input n_t_20x;
inout n_t_21x;
inout n_t_22x;
input n_t_23x;
input n_t_24x;
inout n_t_25x;
inout n_t_26x;
input n_t_27x;
input n_t_28x;
inout n_t_29x;
inout n_t_2x;
inout n_t_30x;
input n_t_31x;
input n_t_32x;
input n_t_3x;
input n_t_4x;
inout n_t_5x;
inout n_t_6x;
input n_t_7x;
input n_t_8x;
inout n_t_9x;


assign n_t_2x = ~(n_t_3x & n_t_1x);
assign n_t_1x = ~(n_t_2x & n_t_4x);
assign n_t_6x = ~(n_t_8x & n_t_5x);
assign n_t_5x = ~(n_t_6x & n_t_7x);
// e2: sn7400 
assign n_t_10x = ~(n_t_11x & n_t_9x);
assign n_t_9x = ~(n_t_10x & n_t_12x);
assign n_t_14x = ~(n_t_16x & n_t_13x);
assign n_t_13x = ~(n_t_14x & n_t_15x);
// e3: sn7400 
assign n_t_18x = ~(n_t_19x & n_t_17x);
assign n_t_17x = ~(n_t_18x & n_t_20x);
assign n_t_22x = ~(n_t_24x & n_t_21x);
assign n_t_21x = ~(n_t_22x & n_t_23x);
// e4: sn7400 
assign n_t_26x = ~(n_t_27x & n_t_25x);
assign n_t_25x = ~(n_t_26x & n_t_28x);
assign n_t_30x = ~(n_t_32x & n_t_29x);
assign n_t_29x = ~(n_t_30x & n_t_31x);
// open collector 'wire-or's 
endmodule