// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// e1: sn7472 
module m204x (n3v3, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_29x, n_t_2x, n_t_30x, n_t_31x, n_t_32x, n_t_34x, n_t_35x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
input n3v3;
input n_t_10x;
output n_t_11x;
input n_t_12x;
input n_t_13x;
input n_t_14x;
inout reg n_t_15x;
input n_t_16x;
input n_t_17x;
input n_t_1x;
input n_t_20x;
input n_t_21x;
input n_t_22x;
input n_t_23x;
input n_t_24x;
input n_t_25x;
input n_t_26x;
inout reg n_t_27x;
input n_t_28x;
input n_t_29x;
input n_t_2x;
inout reg n_t_30x;
output n_t_31x;
input n_t_32x;
input n_t_34x;
input n_t_35x;
input n_t_3x;
input n_t_4x;
input n_t_5x;
output n_t_6x;
inout reg n_t_7x;
output n_t_8x;
input n_t_9x;

reg n_t_15x_m;
reg n_t_27x_m;
reg n_t_30x_m;
reg n_t_7x_m;

always @(n_t_12x, n_t_2x, n_t_9x, n_t_14x, n_t_10x, n3v3, n_t_13x, n3v3, n3v3, n_t_15x)
  if (~n_t_2x) begin
    n_t_15x_m <= 1'b0;
  end else
  if (~n_t_9x) begin
    n_t_15x_m <= 1'b1;
  end else
  if (~(n_t_12x)) begin
    n_t_15x_m <= n_t_14x & n_t_10x & n3v3? (n_t_13x & n3v3 & n3v3? ~n_t_15x: 1'b1) : (n_t_13x & n3v3 & n3v3? 1'b0: n_t_15x);
  end
always @(n_t_12x, n_t_2x, n_t_9x, n_t_15x_m)
  if (~n_t_2x) begin
    n_t_15x <= 1'b0;
  end else
  if (~n_t_9x) begin
    n_t_15x <= 1'b1;
  end else
  if (n_t_12x) begin
    n_t_15x <= n_t_15x_m;
  end
assign n_t_11x = ~n_t_15x;
// e2: sn7472 
always @(n_t_4x, n_t_2x, n_t_1x, n3v3, n_t_3x, n_t_5x, n3v3, n3v3, n_t_7x)
  if (~n_t_2x) begin
    n_t_7x_m <= 1'b0;
  end else
  if (~n_t_1x) begin
    n_t_7x_m <= 1'b1;
  end else
  if (~(n_t_4x)) begin
    n_t_7x_m <= n3v3 & n_t_3x? (n_t_5x & n3v3 & n3v3? ~n_t_7x: 1'b1) : (n_t_5x & n3v3 & n3v3? 1'b0: n_t_7x);
  end
always @(n_t_4x, n_t_2x, n_t_1x, n_t_7x_m)
  if (~n_t_2x) begin
    n_t_7x <= 1'b0;
  end else
  if (~n_t_1x) begin
    n_t_7x <= 1'b1;
  end else
  if (n_t_4x) begin
    n_t_7x <= n_t_7x_m;
  end
assign n_t_6x = ~n_t_7x;
// e3: sn7472 
always @(n_t_35x, n_t_2x, n_t_34x, n_t_28x, n_t_29x, n3v3, n_t_17x, n_t_32x, n3v3, n_t_30x)
  if (~n_t_2x) begin
    n_t_30x_m <= 1'b0;
  end else
  if (~n_t_34x) begin
    n_t_30x_m <= 1'b1;
  end else
  if (~(n_t_35x)) begin
    n_t_30x_m <= n_t_28x & n_t_29x & n3v3? (n_t_17x & n_t_32x & n3v3? ~n_t_30x: 1'b1) : (n_t_17x & n_t_32x & n3v3? 1'b0: n_t_30x);
  end
always @(n_t_35x, n_t_2x, n_t_34x, n_t_30x_m)
  if (~n_t_2x) begin
    n_t_30x <= 1'b0;
  end else
  if (~n_t_34x) begin
    n_t_30x <= 1'b1;
  end else
  if (n_t_35x) begin
    n_t_30x <= n_t_30x_m;
  end
assign n_t_31x = ~n_t_30x;
// e4: sn7472 
always @(n_t_23x, n_t_2x, n_t_20x, n_t_21x, n_t_22x, n_t_16x, n_t_24x, n_t_26x, n_t_25x, n_t_27x)
  if (~n_t_2x) begin
    n_t_27x_m <= 1'b0;
  end else
  if (~n_t_20x) begin
    n_t_27x_m <= 1'b1;
  end else
  if (~(n_t_23x)) begin
    n_t_27x_m <= n_t_21x & n_t_22x & n_t_16x? (n_t_24x & n_t_26x & n_t_25x? ~n_t_27x: 1'b1) : (n_t_24x & n_t_26x & n_t_25x? 1'b0: n_t_27x);
  end
always @(n_t_23x, n_t_2x, n_t_20x, n_t_27x_m)
  if (~n_t_2x) begin
    n_t_27x <= 1'b0;
  end else
  if (~n_t_20x) begin
    n_t_27x <= 1'b1;
  end else
  if (n_t_23x) begin
    n_t_27x <= n_t_27x_m;
  end
assign n_t_8x = ~n_t_27x;
// open collector 'wire-or's 
endmodule