// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// e1: sn7474 
module m205a (n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_23x, n_t_24x, n_t_25x, n_t_26x, n_t_27x, n_t_28x, n_t_29x, n_t_2x, n_t_30x, n_t_31x, n_t_32x, n_t_3x, n_t_4x, n_t_5x, n_t_6x, n_t_7x, n_t_8x, n_t_9x);
input n_t_10x;
input n_t_11x;
input n_t_12x;
output n_t_13x;
inout reg n_t_14x;
input n_t_15x;
input n_t_16x;
input n_t_17x;
output n_t_18x;
inout reg n_t_19x;
output n_t_1x;
input n_t_20x;
input n_t_21x;
input n_t_22x;
input n_t_23x;
output n_t_24x;
inout reg n_t_25x;
input n_t_26x;
input n_t_27x;
input n_t_28x;
input n_t_29x;
output n_t_2x;
input n_t_30x;
inout reg n_t_31x;
output n_t_32x;
output n_t_3x;
inout reg n_t_4x;
input n_t_5x;
input n_t_6x;
input n_t_7x;
input n_t_8x;
input n_t_9x;

reg n_t_14x_m;
reg n_t_19x_m;
reg n_t_25x_m;
reg n_t_31x_m;
reg n_t_4x_m;

always @(n_t_7x, n_t_8x, n_t_6x, n_t_5x)
  if (~n_t_8x) begin
    n_t_4x_m <= 1'b0;
  end else
  if (~n_t_6x) begin
    n_t_4x_m <= 1'b1;
  end else
  if (~(n_t_7x)) begin
    n_t_4x_m <= n_t_5x;
  end
always @(n_t_7x, n_t_8x, n_t_6x, n_t_4x_m)
  if (~n_t_8x) begin
    n_t_4x <= 1'b0;
  end else
  if (~n_t_6x) begin
    n_t_4x <= 1'b1;
  end else
  if (n_t_7x) begin
    n_t_4x <= n_t_4x_m;
  end
assign n_t_3x = ~n_t_4x;
always @(n_t_22x, n_t_21x, n_t_23x, n_t_26x)
  if (~n_t_21x) begin
    n_t_25x_m <= 1'b0;
  end else
  if (~n_t_23x) begin
    n_t_25x_m <= 1'b1;
  end else
  if (~(n_t_22x)) begin
    n_t_25x_m <= n_t_26x;
  end
always @(n_t_22x, n_t_21x, n_t_23x, n_t_25x_m)
  if (~n_t_21x) begin
    n_t_25x <= 1'b0;
  end else
  if (~n_t_23x) begin
    n_t_25x <= 1'b1;
  end else
  if (n_t_22x) begin
    n_t_25x <= n_t_25x_m;
  end
assign n_t_24x = ~n_t_25x;
// e2: sn7474 
always @(n_t_10x, n_t_9x, n_t_12x, n_t_11x)
  if (~n_t_9x) begin
    n_t_14x_m <= 1'b0;
  end else
  if (~n_t_12x) begin
    n_t_14x_m <= 1'b1;
  end else
  if (~(n_t_10x)) begin
    n_t_14x_m <= n_t_11x;
  end
always @(n_t_10x, n_t_9x, n_t_12x, n_t_14x_m)
  if (~n_t_9x) begin
    n_t_14x <= 1'b0;
  end else
  if (~n_t_12x) begin
    n_t_14x <= 1'b1;
  end else
  if (n_t_10x) begin
    n_t_14x <= n_t_14x_m;
  end
assign n_t_13x = ~n_t_14x;
always @(n_t_28x, n_t_27x, n_t_30x, n_t_29x)
  if (~n_t_27x) begin
    n_t_31x_m <= 1'b0;
  end else
  if (~n_t_30x) begin
    n_t_31x_m <= 1'b1;
  end else
  if (~(n_t_28x)) begin
    n_t_31x_m <= n_t_29x;
  end
always @(n_t_28x, n_t_27x, n_t_30x, n_t_31x_m)
  if (~n_t_27x) begin
    n_t_31x <= 1'b0;
  end else
  if (~n_t_30x) begin
    n_t_31x <= 1'b1;
  end else
  if (n_t_28x) begin
    n_t_31x <= n_t_31x_m;
  end
assign n_t_32x = ~n_t_31x;
// e3: sn7474 
always @(n_t_16x, n_t_15x, n_t_20x, n_t_17x)
  if (~n_t_15x) begin
    n_t_19x_m <= 1'b0;
  end else
  if (~n_t_20x) begin
    n_t_19x_m <= 1'b1;
  end else
  if (~(n_t_16x)) begin
    n_t_19x_m <= n_t_17x;
  end
always @(n_t_16x, n_t_15x, n_t_20x, n_t_19x_m)
  if (~n_t_15x) begin
    n_t_19x <= 1'b0;
  end else
  if (~n_t_20x) begin
    n_t_19x <= 1'b1;
  end else
  if (n_t_16x) begin
    n_t_19x <= n_t_19x_m;
  end
assign n_t_18x = ~n_t_19x;
// open collector 'wire-or's 
endmodule