// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// e1: sn7474 
module m206c (ff1, ff2, a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input ff1;
input ff2;
input a1;
input b1;
input c1;
input d1;
input d2;
inout reg e1;
input e2;
output f1;
input f2;
input h1;
inout reg h2;
input j1;
output j2;
input k1;
input k2;
inout reg l1;
input l2;
output m1;
input m2;
input n1;
input n2;
input p1;
inout reg p2;
input r1;
output r2;
inout reg s1;
input s2;
input t2;
output u1;
input u2;
output v1;
inout reg v2;

reg e1_m;
reg h2_m;
reg l1_m;
reg p2_m;
reg s1_m;
reg v2_m;

always @(b1, a1, d1, c1)
  if (~a1) begin
    e1_m <= 1'b0;
  end else
  if (~d1) begin
    e1_m <= 1'b1;
  end else
  if (~(b1)) begin
    e1_m <= c1;
  end
always @(b1, a1, d1, e1_m)
  if (~a1) begin
    e1 <= 1'b0;
  end else
  if (~d1) begin
    e1 <= 1'b1;
  end else
  if (b1) begin
    e1 <= e1_m;
  end
assign f1 = ~e1;
always @(d2, ff1, f2, e2)
  if (~ff1) begin
    h2_m <= 1'b0;
  end else
  if (~f2) begin
    h2_m <= 1'b1;
  end else
  if (~(d2)) begin
    h2_m <= e2;
  end
always @(d2, ff1, f2, h2_m)
  if (~ff1) begin
    h2 <= 1'b0;
  end else
  if (~f2) begin
    h2 <= 1'b1;
  end else
  if (d2) begin
    h2 <= h2_m;
  end
assign j2 = ~h2;
// e2: sn7474 
always @(h1, ff2, k1, j1)
  if (~ff2) begin
    l1_m <= 1'b0;
  end else
  if (~k1) begin
    l1_m <= 1'b1;
  end else
  if (~(h1)) begin
    l1_m <= j1;
  end
always @(h1, ff2, k1, l1_m)
  if (~ff2) begin
    l1 <= 1'b0;
  end else
  if (~k1) begin
    l1 <= 1'b1;
  end else
  if (h1) begin
    l1 <= l1_m;
  end
assign m1 = ~l1;
always @(l2, k2, n2, m2)
  if (~k2) begin
    p2_m <= 1'b0;
  end else
  if (~n2) begin
    p2_m <= 1'b1;
  end else
  if (~(l2)) begin
    p2_m <= m2;
  end
always @(l2, k2, n2, p2_m)
  if (~k2) begin
    p2 <= 1'b0;
  end else
  if (~n2) begin
    p2 <= 1'b1;
  end else
  if (l2) begin
    p2 <= p2_m;
  end
assign r2 = ~p2;
// e3: sn7474 
always @(n1, k2, r1, p1)
  if (~k2) begin
    s1_m <= 1'b0;
  end else
  if (~r1) begin
    s1_m <= 1'b1;
  end else
  if (~(n1)) begin
    s1_m <= p1;
  end
always @(n1, k2, r1, s1_m)
  if (~k2) begin
    s1 <= 1'b0;
  end else
  if (~r1) begin
    s1 <= 1'b1;
  end else
  if (n1) begin
    s1 <= s1_m;
  end
assign u1 = ~s1;
always @(s2, k2, u2, t2)
  if (~k2) begin
    v2_m <= 1'b0;
  end else
  if (~u2) begin
    v2_m <= 1'b1;
  end else
  if (~(s2)) begin
    v2_m <= t2;
  end
always @(s2, k2, u2, v2_m)
  if (~k2) begin
    v2 <= 1'b0;
  end else
  if (~u2) begin
    v2 <= 1'b1;
  end else
  if (s2) begin
    v2 <= v2_m;
  end
assign v1 = ~v2;
// open collector 'wire-or's 
endmodule