// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// e1: sn7474 
module m208c (n3v3, a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input n3v3;
input a1;
input b1;
inout reg c1;
input d1;
output d2;
inout reg e1;
input e2;
input f1;
output f2;
inout reg h1;
input h2;
input j1;
inout j2;
inout reg k1;
input k2;
input l1;
inout l2;
inout reg m1;
input m2;
input n1;
output n2;
inout reg p1;
input p2;
input r1;
inout r2;
input s1;
inout reg s2;
inout t2;
inout reg u1;
input u2;
input v1;
inout v2;

reg c1_m;
reg e1_m;
reg h1_m;
reg k1_m;
reg m1_m;
reg p1_m;
reg s2_m;
reg u1_m;

wire n_t_14x;
wire n_t_1x;
wire n_t_27x;
wire n_t_2x;
wire n_t_31x;
wire n_t_32x;
wire n_t_3x;
wire n_t_4x;
wire n_t_5x;
wire n_t_6x;
wire n_t_7x;
wire n_t_8x;
wire n_t_9x;
always @(n_t_27x, n_t_32x, n_t_7x)
  if (~n_t_32x) begin
    e1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    e1_m <= n_t_7x;
  end
always @(n_t_27x, n_t_32x, e1_m)
  if (~n_t_32x) begin
    e1 <= 1'b1;
  end else
  if (n_t_27x) begin
    e1 <= e1_m;
  end
assign f2 = ~e1;
always @(n_t_27x, n_t_32x, n_t_8x)
  if (~n_t_32x) begin
    c1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    c1_m <= n_t_8x;
  end
always @(n_t_27x, n_t_32x, c1_m)
  if (~n_t_32x) begin
    c1 <= 1'b1;
  end else
  if (n_t_27x) begin
    c1 <= c1_m;
  end
assign d2 = ~c1;
// e2: sn7450 
assign n_t_8x = ~(n_t_9x & d1
                   | h2 & n_t_14x);
assign n_t_7x = ~(n_t_9x & f1
                   | j2 & n_t_14x);
// e3: sn7474 
always @(n_t_27x, n_t_32x, n_t_5x)
  if (~n_t_32x) begin
    k1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    k1_m <= n_t_5x;
  end
always @(n_t_27x, n_t_32x, k1_m)
  if (~n_t_32x) begin
    k1 <= 1'b1;
  end else
  if (n_t_27x) begin
    k1 <= k1_m;
  end
assign l2 = ~k1;
always @(n_t_27x, n_t_32x, n_t_6x)
  if (~n_t_32x) begin
    h1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    h1_m <= n_t_6x;
  end
always @(n_t_27x, n_t_32x, h1_m)
  if (~n_t_32x) begin
    h1 <= 1'b1;
  end else
  if (n_t_27x) begin
    h1 <= h1_m;
  end
assign j2 = ~h1;
// e4: sn7450 
assign n_t_6x = ~(n_t_9x & j1
                   | l2 & n_t_14x);
assign n_t_5x = ~(n_t_9x & l1
                   | p2 & n_t_14x);
// e5: sn7400 
assign n_t_31x = ~(n3v3 & b1);
assign n_t_14x = ~(k2 & n3v3);
assign n_t_9x = ~(m2 & n3v3);
assign n_t_32x = ~(n3v3 & b1);
// e6: sn74h40 
assign n_t_27x = ~(a1 & u2);
// e7: sn7474 
always @(n_t_27x, n_t_31x, n_t_1x)
  if (~n_t_31x) begin
    u1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    u1_m <= n_t_1x;
  end
always @(n_t_27x, n_t_31x, u1_m)
  if (~n_t_31x) begin
    u1 <= 1'b1;
  end else
  if (n_t_27x) begin
    u1 <= u1_m;
  end
assign v2 = ~u1;
always @(n_t_27x, n_t_31x, n_t_2x)
  if (~n_t_31x) begin
    s2_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    s2_m <= n_t_2x;
  end
always @(n_t_27x, n_t_31x, s2_m)
  if (~n_t_31x) begin
    s2 <= 1'b1;
  end else
  if (n_t_27x) begin
    s2 <= s2_m;
  end
assign t2 = ~s2;
// e8: sn7450 
assign n_t_2x = ~(n_t_9x & s1
                   | v2 & n_t_14x);
assign n_t_1x = ~(n_t_9x & v1
                   | e2 & n_t_14x);
// e9: sn7474 
always @(n_t_27x, n_t_31x, n_t_3x)
  if (~n_t_31x) begin
    p1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    p1_m <= n_t_3x;
  end
always @(n_t_27x, n_t_31x, p1_m)
  if (~n_t_31x) begin
    p1 <= 1'b1;
  end else
  if (n_t_27x) begin
    p1 <= p1_m;
  end
assign r2 = ~p1;
always @(n_t_27x, n_t_31x, n_t_4x)
  if (~n_t_31x) begin
    m1_m <= 1'b1;
  end else
  if (~(n_t_27x)) begin
    m1_m <= n_t_4x;
  end
always @(n_t_27x, n_t_31x, m1_m)
  if (~n_t_31x) begin
    m1 <= 1'b1;
  end else
  if (n_t_27x) begin
    m1 <= m1_m;
  end
assign n2 = ~m1;
// e10: sn7450 
assign n_t_4x = ~(n_t_9x & n1
                   | r2 & n_t_14x);
assign n_t_3x = ~(n_t_9x & r1
                   | t2 & n_t_14x);
// open collector 'wire-or's 
endmodule