// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// e1: sn7453 
// gdollar_0 = !(sr_insert & right_shift
//          # ina0_l & enable_a
//          # inb0_l & enable_b
//          # n_t_10x & left_shift); 
// !gdollar_0 = !gdollar_0; 
// e2: sn7453 
// gdollar_2 = !(n_t_8x & right_shift
//          # ina1_l & enable_a
//          # inb1_l & enable_b
//          # n_t_12x & left_shift); 
// !gdollar_2 = !gdollar_2; 
// e3: sn7474 
module m212b (n3v3, clear_reg_l, clock, enable_a, enable_b, ina0_l, ina1_l, ina2_l, ina3_l, ina4_l, ina5_l, inb0_l, inb1_l, inb2_l, inb3_l, inb4_l, inb5_l, left_shift, n_t_10x, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_7x, n_t_8x, n_t_9x, right_shift, sl_insert, sr_insert);
input n3v3;
input clear_reg_l;
input clock;
input enable_a;
input enable_b;
input ina0_l;
input ina1_l;
input ina2_l;
input ina3_l;
input ina4_l;
input ina5_l;
input inb0_l;
input inb1_l;
input inb2_l;
input inb3_l;
input inb4_l;
input inb5_l;
input left_shift;
inout n_t_10x;
inout reg n_t_11x;
inout n_t_12x;
inout reg n_t_13x;
inout n_t_14x;
inout reg n_t_15x;
inout n_t_16x;
inout reg n_t_17x;
inout n_t_18x;
inout reg n_t_7x;
inout n_t_8x;
inout reg n_t_9x;
input right_shift;
input sl_insert;
input sr_insert;

reg n_t_11x_m;
reg n_t_13x_m;
reg n_t_15x_m;
reg n_t_17x_m;
reg n_t_7x_m;
reg n_t_9x_m;

always @(clock, n3v3, clear_reg_l, gdollar_0)
  if (~n3v3) begin
    n_t_7x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_7x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_7x_m <= gdollar_0;
  end
always @(clock, n3v3, clear_reg_l, n_t_7x_m)
  if (~n3v3) begin
    n_t_7x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_7x <= 1'b1;
  end else
  if (clock) begin
    n_t_7x <= n_t_7x_m;
  end
assign n_t_8x = ~n_t_7x;
always @(clock, n3v3, clear_reg_l, gdollar_2)
  if (~n3v3) begin
    n_t_9x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_9x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_9x_m <= gdollar_2;
  end
always @(clock, n3v3, clear_reg_l, n_t_9x_m)
  if (~n3v3) begin
    n_t_9x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_9x <= 1'b1;
  end else
  if (clock) begin
    n_t_9x <= n_t_9x_m;
  end
assign n_t_10x = ~n_t_9x;
// e4: sn7453 
// gdollar_4 = !(n_t_10x & right_shift
//          # ina2_l & enable_a
//          # inb2_l & enable_b
//          # n_t_14x & left_shift); 
// !gdollar_4 = !gdollar_4; 
// e5: sn7453 
// gdollar_6 = !(n_t_12x & right_shift
//          # ina3_l & enable_a
//          # inb3_l & enable_b
//          # n_t_16x & left_shift); 
// !gdollar_6 = !gdollar_6; 
// e6: sn7474 
always @(clock, n3v3, clear_reg_l, gdollar_4)
  if (~n3v3) begin
    n_t_11x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_11x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_11x_m <= gdollar_4;
  end
always @(clock, n3v3, clear_reg_l, n_t_11x_m)
  if (~n3v3) begin
    n_t_11x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_11x <= 1'b1;
  end else
  if (clock) begin
    n_t_11x <= n_t_11x_m;
  end
assign n_t_12x = ~n_t_11x;
always @(clock, n3v3, clear_reg_l, gdollar_6)
  if (~n3v3) begin
    n_t_13x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_13x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_13x_m <= gdollar_6;
  end
always @(clock, n3v3, clear_reg_l, n_t_13x_m)
  if (~n3v3) begin
    n_t_13x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_13x <= 1'b1;
  end else
  if (clock) begin
    n_t_13x <= n_t_13x_m;
  end
assign n_t_14x = ~n_t_13x;
// e7: sn7453 
// gdollar_8 = !(n_t_14x & right_shift
//          # ina4_l & enable_a
//          # inb4_l & enable_b
//          # n_t_18x & left_shift); 
// !gdollar_8 = !gdollar_8; 
// e8: sn7453 
// gdollar_10 = !(n_t_16x & right_shift
//           # ina5_l & enable_a
//           # inb5_l & enable_b
//           # sl_insert & left_shift); 
// !gdollar_10 = !gdollar_10; 
// e9: sn7474 
always @(clock, n3v3, clear_reg_l, gdollar_8)
  if (~n3v3) begin
    n_t_15x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_15x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_15x_m <= gdollar_8;
  end
always @(clock, n3v3, clear_reg_l, n_t_15x_m)
  if (~n3v3) begin
    n_t_15x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_15x <= 1'b1;
  end else
  if (clock) begin
    n_t_15x <= n_t_15x_m;
  end
assign n_t_16x = ~n_t_15x;
always @(clock, n3v3, clear_reg_l, gdollar_10)
  if (~n3v3) begin
    n_t_17x_m <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_17x_m <= 1'b1;
  end else
  if (~(clock)) begin
    n_t_17x_m <= gdollar_10;
  end
always @(clock, n3v3, clear_reg_l, n_t_17x_m)
  if (~n3v3) begin
    n_t_17x <= 1'b0;
  end else
  if (~clear_reg_l) begin
    n_t_17x <= 1'b1;
  end else
  if (clock) begin
    n_t_17x <= n_t_17x_m;
  end
assign n_t_18x = ~n_t_17x;
// open collector 'wire-or's 
assign gdollar_0 = ~((sr_insert & right_shift
                       | ina0_l & enable_a
                       | inb0_l & enable_b
                       | n_t_10x & left_shift));
assign gdollar_10 = ~((n_t_16x & right_shift
                        | ina5_l & enable_a
                        | inb5_l & enable_b
                        | sl_insert & left_shift));
assign gdollar_2 = ~((n_t_8x & right_shift
                       | ina1_l & enable_a
                       | inb1_l & enable_b
                       | n_t_12x & left_shift));
assign gdollar_4 = ~((n_t_10x & right_shift
                       | ina2_l & enable_a
                       | inb2_l & enable_b
                       | n_t_14x & left_shift));
assign gdollar_6 = ~((n_t_12x & right_shift
                       | ina3_l & enable_a
                       | inb3_l & enable_b
                       | n_t_16x & left_shift));
assign gdollar_8 = ~((n_t_14x & right_shift
                       | ina4_l & enable_a
                       | inb4_l & enable_b
                       | n_t_18x & left_shift));
endmodule