Exported from /home/vrs/Eagle/projects/DEC/Mxxx/M212/M212B.sch Part Pad Pin Dir Net C1 1 1 pas +3V3 2 2 pas GND C2 1 1 pas VCC 2 2 pas GND C3 1 1 pas VCC 2 2 pas GND C4 1 1 pas VCC 2 2 pas GND C5 1 1 pas VCC 2 2 pas GND C6 1 1 pas VCC 2 2 pas GND C7 1 1 pas VCC 2 2 pas GND C8 1 1 pas VCC 2 2 pas GND C9 1 1 pas VCC 2 2 pas GND C10 1 1 pas VCC 2 2 pas GND E1 1 I4 in SR_INSERT 2 I5 in !INA0 3 I6 in ENABLE_A 4 I1 in !INB0 5 I2 in ENABLE_B 8 O out N$1 9 I8 in N$10 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E2 1 I4 in N$8 2 I5 in !INA1 3 I6 in ENABLE_A 4 I1 in !INB1 5 I2 in ENABLE_B 8 O out N$2 9 I8 in N$12 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E3 1 CLR in +3V3 2 D in N$1 3 CLK in CLOCK 4 PRE in !CLEAR_REG 5 Q out N$7 6 !Q out N$8 8 !Q out N$10 9 Q out N$9 10 PRE in !CLEAR_REG 11 CLK in CLOCK 12 D in N$2 13 CLR in +3V3 E4 1 I4 in N$10 2 I5 in !INA2 3 I6 in ENABLE_A 4 I1 in !INB2 5 I2 in ENABLE_B 8 O out N$3 9 I8 in N$14 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E5 1 I4 in N$12 2 I5 in !INA3 3 I6 in ENABLE_A 4 I1 in !INB3 5 I2 in ENABLE_B 8 O out N$4 9 I8 in N$16 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E6 1 CLR in +3V3 2 D in N$3 3 CLK in CLOCK 4 PRE in !CLEAR_REG 5 Q out N$11 6 !Q out N$12 8 !Q out N$14 9 Q out N$13 10 PRE in !CLEAR_REG 11 CLK in CLOCK 12 D in N$4 13 CLR in +3V3 E7 1 I4 in N$14 2 I5 in !INA4 3 I6 in ENABLE_A 4 I1 in !INB4 5 I2 in ENABLE_B 8 O out N$5 9 I8 in N$18 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E8 1 I4 in N$16 2 I5 in !INA5 3 I6 in ENABLE_A 4 I1 in !INB5 5 I2 in ENABLE_B 8 O out N$6 9 I8 in SL_INSERT 10 I7 in LEFT_SHIFT 13 I3 in RIGHT_SHIFT E9 1 CLR in +3V3 2 D in N$5 3 CLK in CLOCK 4 PRE in !CLEAR_REG 5 Q out N$15 6 !Q out N$16 8 !Q out N$18 9 Q out N$17 10 PRE in !CLEAR_REG 11 CLK in CLOCK 12 D in N$6 13 CLR in +3V3 EDGE1 A1 1 io !INB4 A2 1 io VCC B1 1 io !CLEAR_REG C1 1 io CLOCK C2 1 io GND D1 1 io N$8 D2 1 io N$7 E1 1 io N$9 E2 1 io N$11 F1 1 io N$10 F2 1 io N$13 H1 1 io N$14 H2 1 io N$12 J1 1 io N$17 J2 1 io N$15 K1 1 io N$18 K2 1 io N$16 L1 1 io RIGHT_SHIFT L2 1 io !INA0 M1 1 io SR_INSERT M2 1 io !INA1 N1 1 io ENABLE_A N2 1 io !INA2 P1 1 io LEFT_SHIFT P2 1 io !INB0 R1 1 io !INB1 R2 1 io !INA3 S1 1 io !INB2 S2 1 io SL_INSERT T1 1 io GND T2 1 io !INB5 U1 1 io !INB3 U2 1 io ENABLE_B V1 1 io !INA4 V2 1 io !INA5 R1 1 1 pas +3V3 2 2 pas VCC R2 1 1 pas GND 2 2 pas +3V3