// this file is generated by topld.pl // please don't edit it. // input pins // output pins // internal nodes // code nodes // equations // c1: c_us // c2: c_us // c3: c_us // c4: c_us // c5: c_us // c6: c_us // c7: c_us // c8: c_us // c9: c_us // c10: c_us // c11: c_us // c12: c_us // e1: sn7450 module m214a (n_t_15x, n_t_16x, n_t_17x, n_t_18x, n_t_19x, n_t_1x, n_t_20x, n_t_21x, n_t_22x, n_t_25x, n_t_26x, n_t_2x, n_t_38x, n_t_39x, n_t_3x, n_t_40x, n_t_41x, n_t_42x, n_t_43x, n_t_47x, n_t_48x, n_t_4x, n_t_55x, n_t_5x, n_t_60x, n_t_61x, n_t_62x, n_t_63x, n_t_64x, n_t_65x, n_t_6x); input n_t_15x; inout reg n_t_16x; inout reg n_t_17x; input n_t_18x; input n_t_19x; input n_t_1x; input n_t_20x; input n_t_21x; output n_t_22x; input n_t_25x; input n_t_26x; input n_t_2x; inout reg n_t_38x; inout reg n_t_39x; input n_t_3x; input n_t_40x; input n_t_41x; input n_t_42x; input n_t_43x; input n_t_47x; input n_t_48x; input n_t_4x; input n_t_55x; input n_t_5x; inout reg n_t_60x; inout reg n_t_61x; input n_t_62x; input n_t_63x; input n_t_64x; input n_t_65x; input n_t_6x; wire n_t_10x; wire n_t_11x; wire n_t_12x; wire n_t_13x; wire n_t_29x; wire n_t_30x; wire n_t_31x; wire n_t_32x; wire n_t_33x; wire n_t_34x; wire n_t_35x; wire n_t_51x; wire n_t_52x; wire n_t_53x; wire n_t_54x; wire n_t_56x; wire n_t_57x; wire n_t_7x; wire n_t_8x; wire n_t_9x; assign n_t_9x = ~(n_t_1x & n_t_4x | n_t_2x & n_t_16x); assign n_t_10x = ~(n_t_5x & n_t_20x | n_t_6x & n_t_21x); // e2: sn7450 assign n_t_8x = ~(n_t_1x & n_t_3x | n_t_2x & n_t_17x); assign n_t_7x = ~(n_t_5x & n_t_18x | n_t_6x & n_t_19x); // e3: sn7482 assign n_t_13x = n_t_11x ^ n_t_10x ^ n_t_9x; assign gdollar_0 = n_t_11x & n_t_10x | n_t_10x & n_t_9x | n_t_11x & n_t_9x; assign n_t_12x = n_t_8x ^ n_t_7x ^ gdollar_0; assign n_t_22x = gdollar_0 & n_t_8x | n_t_8x & n_t_7x | n_t_7x & gdollar_0; // e4: sn7474 always @(posedge n_t_15x) if (n_t_15x) begin n_t_17x <= ~n_t_12x; end always @(posedge n_t_15x) if (n_t_15x) begin n_t_16x <= ~n_t_13x; end // e5: sn7450 assign n_t_31x = ~(n_t_1x & n_t_26x | n_t_2x & n_t_38x); assign n_t_32x = ~(n_t_5x & n_t_42x | n_t_6x & n_t_43x); // e6: sn7450 assign n_t_30x = ~(n_t_1x & n_t_25x | n_t_2x & n_t_39x); assign n_t_29x = ~(n_t_5x & n_t_40x | n_t_6x & n_t_41x); // e7: sn7482 assign n_t_35x = n_t_33x ^ n_t_32x ^ n_t_31x; assign gdollar_1 = n_t_33x & n_t_32x | n_t_32x & n_t_31x | n_t_33x & n_t_31x; assign n_t_34x = n_t_30x ^ n_t_29x ^ gdollar_1; assign n_t_11x = gdollar_1 & n_t_30x | n_t_30x & n_t_29x | n_t_29x & gdollar_1; // e8: sn7474 always @(posedge n_t_15x) if (n_t_15x) begin n_t_39x <= ~n_t_34x; end always @(posedge n_t_15x) if (n_t_15x) begin n_t_38x <= ~n_t_35x; end // e9: sn7450 assign n_t_53x = ~(n_t_1x & n_t_48x | n_t_2x & n_t_60x); assign n_t_54x = ~(n_t_5x & n_t_64x | n_t_6x & n_t_65x); // e10: sn7450 assign n_t_52x = ~(n_t_1x & n_t_47x | n_t_2x & n_t_61x); assign n_t_51x = ~(n_t_5x & n_t_62x | n_t_6x & n_t_63x); // e11: sn7482 assign n_t_57x = n_t_55x ^ n_t_54x ^ n_t_53x; assign gdollar_2 = n_t_55x & n_t_54x | n_t_54x & n_t_53x | n_t_55x & n_t_53x; assign n_t_56x = n_t_52x ^ n_t_51x ^ gdollar_2; assign n_t_33x = gdollar_2 & n_t_52x | n_t_52x & n_t_51x | n_t_51x & gdollar_2; // e12: sn7474 always @(posedge n_t_15x) if (n_t_15x) begin n_t_61x <= ~n_t_56x; end always @(posedge n_t_15x) if (n_t_15x) begin n_t_60x <= ~n_t_57x; end // open collector 'wire-or's endmodule