// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: cpol_use 
// e1: sn7482 
module m215a (a1, b1, c1, d1, d2, e1, e2, f1, f2, h1, h2, j1, j2, k1, k2, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, s1, s2, t2, u1, u2, v1, v2);
input a1;
input b1;
input c1;
input d1;
output reg d2;
input e1;
output reg e2;
inout f1;
output reg f2;
input h1;
output reg h2;
input j1;
output reg j2;
inout k1;
output reg k2;
input l1;
output reg l2;
input m1;
output reg m2;
inout n1;
output reg n2;
input p1;
output reg p2;
input r1;
output reg r2;
inout s1;
output reg s2;
input t2;
input u1;
input u2;
inout v1;
output v2;

reg e2_m;
reg f2_m;
reg j2_m;
reg k2_m;
reg m2_m;
reg n2_m;
reg r2_m;
reg s2_m;

assign f1 = u1
             ^ d1
             ^ e1;
assign gdollar_0 = u1 & d1
                    | d1 & e1
                    | u1 & e1;
assign k1 = j1
             ^ h1
             ^ gdollar_0;
assign v1 = gdollar_0 & j1
             | j1 & h1
             | h1 & gdollar_0;
// e2: sn7474 
always @(c1, u2, f1)
  if (~u2) begin
    f2_m <= 1'b0;
  end else
  if (~(c1)) begin
    f2_m <= f1;
  end
always @(c1, u2, f2_m)
  if (~u2) begin
    f2 <= 1'b0;
  end else
  if (c1) begin
    f2 <= f2_m;
  end
always @(b1, t2, f1)
  if (~t2) begin
    e2_m <= 1'b0;
  end else
  if (~(b1)) begin
    e2_m <= f1;
  end
always @(b1, t2, e2_m)
  if (~t2) begin
    e2 <= 1'b0;
  end else
  if (b1) begin
    e2 <= e2_m;
  end
// e3: sn7474 
always @(posedge a1)
  if (a1) begin
    h2 <= k1;
  end
always @(posedge a1)
  if (a1) begin
    d2 <= f1;
  end
// e4: sn7474 
always @(posedge a1)
  if (a1) begin
    l2 <= n1;
  end
always @(c1, u2, k1)
  if (~u2) begin
    k2_m <= 1'b0;
  end else
  if (~(c1)) begin
    k2_m <= k1;
  end
always @(c1, u2, k2_m)
  if (~u2) begin
    k2 <= 1'b0;
  end else
  if (c1) begin
    k2 <= k2_m;
  end
// e5: sn7474 
always @(b1, t2, n1)
  if (~t2) begin
    m2_m <= 1'b0;
  end else
  if (~(b1)) begin
    m2_m <= n1;
  end
always @(b1, t2, m2_m)
  if (~t2) begin
    m2 <= 1'b0;
  end else
  if (b1) begin
    m2 <= m2_m;
  end
always @(b1, t2, k1)
  if (~t2) begin
    j2_m <= 1'b0;
  end else
  if (~(b1)) begin
    j2_m <= k1;
  end
always @(b1, t2, j2_m)
  if (~t2) begin
    j2 <= 1'b0;
  end else
  if (b1) begin
    j2 <= j2_m;
  end
// e6: sn7482 
assign n1 = v1
             ^ l1
             ^ m1;
assign gdollar_1 = v1 & l1
                    | l1 & m1
                    | v1 & m1;
assign s1 = r1
             ^ p1
             ^ gdollar_1;
assign v2 = gdollar_1 & r1
             | r1 & p1
             | p1 & gdollar_1;
// e7: sn7474 
always @(b1, t2, s1)
  if (~t2) begin
    r2_m <= 1'b0;
  end else
  if (~(b1)) begin
    r2_m <= s1;
  end
always @(b1, t2, r2_m)
  if (~t2) begin
    r2 <= 1'b0;
  end else
  if (b1) begin
    r2 <= r2_m;
  end
always @(posedge a1)
  if (a1) begin
    p2 <= s1;
  end
// e8: sn7474 
always @(c1, u2, s1)
  if (~u2) begin
    s2_m <= 1'b0;
  end else
  if (~(c1)) begin
    s2_m <= s1;
  end
always @(c1, u2, s2_m)
  if (~u2) begin
    s2 <= 1'b0;
  end else
  if (c1) begin
    s2 <= s2_m;
  end
always @(c1, u2, n1)
  if (~u2) begin
    n2_m <= 1'b0;
  end else
  if (~(c1)) begin
    n2_m <= n1;
  end
always @(c1, u2, n2_m)
  if (~u2) begin
    n2 <= 1'b0;
  end else
  if (c1) begin
    n2 <= n2_m;
  end
// open collector 'wire-or's 
endmodule